SET response of a SEL protection switch for 130 and 250 nm CMOS technologies

This paper analyzes the single event transient (SET) response of a single event latchup (SEL) protection switch (SPS) designed in the 130 and 250 nm bulk CMOS technologies. The analysis has been conducted through the SPICE simulations, using the standard double exponential current source as the SET model. It has been confirmed that the 130 nm SPS cell is more susceptible to SETs than the 250 nm version, i.e. the 130 nm SPS cell has exhibited significantly lower critical charge. Based on the simulation results, an analytical model for estimating the critical charge in terms of the transistor size, number of load cells, and duration of the SET current pulse, has been derived. Use of the proposed critical charge model simplifies the analysis of the SPS cell's susceptibility to SETs for custom designs.