Comparison of RTL fault models for the robustness evaluation of aerospace FPGA devices

Abstract

Confronted to more and more demanding standards in terms of safety and reliability, aerospace companies are investigating new methodologies to evaluate the robustness of their FPGA designs against energetic particles. In this paper, this evaluation is realized early in the design flow to avoid costly design re-spins. It permits to have a first evaluation of the RTL design robustness and of the design protections efficiency. To deal with the low accuracy of classical RTL fault models, we use a new RTL fault model taking into account the local effects of particles. We compare the fault model characteristics of different high level fault models (RTL) and low level fault models (layout) on a RTL design dedicated to the plane power supply control. These evaluations show that the new RTL fault model have best characteristics than the classical register fault model.