ISA-independent post-silicon validation for the address translation mechanisms of modern microprocessors

G. Papadimitriou, Athanasios Chatzidimitriou, D. Gizopoulos, Ronny Morad
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引用次数: 1

Abstract

Post-silicon validation complements traditional simulation-based pre-silicon verification and offers very high throughput since validation programs run at the speed of the actual hardware. Detection of bugs in the address translation subsystem of a microprocessor is much less straightforward than other hardware blocks because the address translation is an implicit process, which does not have an easily observable output to architecture or program visible locations. Validation of the correctness of the address translation mechanisms (ATMs) of microprocessors is both very important and challenging problem. In this paper, we present an ISA-independent methodology for the post-silicon validation of the ATMs in modern microprocessors. We first capture the effects of design bugs in address translation, by presenting actual bugs scenarios reported for commercial chips. We also describe an effective method for the detection of bugs in all address translation hardware blocks. The validation programs of the method are self-checking, i.e. do not require a bug-free model to compare with. Our experimental evaluation on Gem5 simulator shows the effectiveness of the methodology in detecting bugs in the address translation hardware of an x86-64 microprocessor model.
现代微处理器地址转换机制的isa独立后硅验证
硅后验证补充了传统的基于仿真的硅前验证,并提供了非常高的吞吐量,因为验证程序以实际硬件的速度运行。在微处理器的地址转换子系统中检测错误比其他硬件块要简单得多,因为地址转换是一个隐式过程,它没有一个容易观察到的输出到体系结构或程序可见位置。验证微处理器地址转换机制(ATMs)的正确性是一个非常重要且具有挑战性的问题。在本文中,我们提出了一种独立于isa的方法,用于现代微处理器中atm的后硅验证。我们首先通过展示商业芯片报告的实际错误场景来捕捉地址转换中设计错误的影响。我们还描述了一种有效的方法来检测所有地址转换硬件块中的错误。该方法的验证程序是自检的,即不需要无bug的模型进行比较。我们在Gem5模拟器上的实验评估表明,该方法在检测x86-64微处理器模型地址转换硬件中的错误方面是有效的。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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