2016 IEEE International Symposium on Circuits and Systems (ISCAS)最新文献_第6页

Construction of the nodal conductance matrix of a planar resistive grid and derivation of the analytical expressions of its eigenvalues and eigenvectors using the Kronecker product and sum 构造了平面电阻网格的节点电导矩阵，并利用Kronecker积和导出了其特征值和特征向量的解析表达式

2016 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2016-05-22 DOI: 10.1109/ISCAS.2016.7527191

V. Tavsanoglu

{"title":"Construction of the nodal conductance matrix of a planar resistive grid and derivation of the analytical expressions of its eigenvalues and eigenvectors using the Kronecker product and sum","authors":"V. Tavsanoglu","doi":"10.1109/ISCAS.2016.7527191","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7527191","url":null,"abstract":"This paper considers the task of constructing an (M×A+1)-node rectangular planar resistive grid as: first forming two (M×A+1)-node planar sub-grids; one made up of M of (N+1)-node horizontal, and the other of N of (M+1)-node vertical linear resistive grids, then joining their corresponding nodes. By doing so it is sho wn that the nodal conductance matrices GH and GV of the two sub-grids can be expressed as the Kronecker products GH = Im ⊗ Gn, Gv = Gm ⊗ In, and G of the resultant planar grid as the Kronecker sum G = Gn ⊕ Gm, where Gm and Im are, respectively, the nodal conductance matrix of a linear resistive grid and the identity matrix, both of size M. Moreover, since the analytical expression s for the eigenvalues and eigenvectors of Gm — which is a symmetric tridiagonal matrix — are well known, this approach enables the derivation of the analytical expressions of the eigenvalues and eigenvectors of Gh, Gv and G in terms of those of Gm and Gn, thereby drastically simplifying their computation and rendering the use of any matrix-inversion-based method unnecessary in the solution of nodal equations of very large grids.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"6 1","pages":"145-148"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83507489","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A power efficient PLL with in-loop-bandwidth spread-spectrum modulation scheme using a charge-based discrete-time loop filter 采用基于电荷的离散时间环路滤波器的环内带宽扩频调制方案的高效功率锁相环

2016 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2016-05-22 DOI: 10.1109/ISCAS.2016.7539163

H. Sun, Kazuki Sobue, K. Hamashita, U. Moon

引用次数: 0

Extended exploration of low granularity back biasing control in 28nm UTBB FD-SOI technology 28nm UTBB FD-SOI技术低粒度反偏控制的扩展探索

2016 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2016-05-22 DOI: 10.1109/ISCAS.2016.7527165

R. Taco, I. Levi, M. Lanuzza, A. Fish

{"title":"Extended exploration of low granularity back biasing control in 28nm UTBB FD-SOI technology","authors":"R. Taco, I. Levi, M. Lanuzza, A. Fish","doi":"10.1109/ISCAS.2016.7527165","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7527165","url":null,"abstract":"Recently, we proposed a low-granularity back-bias control technique [1] optimized for the ultra-thin body and box (UTBB) fully-depleted silicon-on-insulator (FD-SOI) technology. The technique was preliminary evaluated through the design of a low-voltage 8-bit ripple carry adder (RCA), showing very competitive energy and delay values. In this paper, the characteristics of the low-granularity back-biasing control are explored considering as benchmarks basic logic gates as well as adders with different bit lengths. All the designed circuits were compared to their equivalent dynamic threshold voltage MOSFE T (DTMOS) and conventional CMOS designs. The higher efficiency of low granularity body bias control is emphasized by the single well layout strategy, offered by the 28 nm UTBB FD-SOI technology, thus leading our approach to achieve competitive silicon area occupancy along with significant performance and energy improvements. More precisely, postlayout simulations have demonstrated that circuits designed according the suggested strategy, can achieve a delay reduction of 33% compared to conventional CMOS designs, whereas the energy consumption can be reduced down to 46% compared to DTMOS solutions, for a supply voltage of 0.4V. These results were obtained while maintaining robustness against process and temperature variations.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"1 1","pages":"41-44"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88623452","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

A calibration-free 96.6-dB-SNDR non-bootstrapped 1.8-V 7.9-mW delta-sigma modulator with class-AB single-stage switched VMAs 无校准96.6 db - sndr非自启动1.8 v 7.9 mw δ - σ调制器，具有ab类单级开关vma

2016 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2016-05-22 DOI: 10.1109/ISCAS.2016.7527170

S. Sutula, M. Dei, L. Terés, F. Serra-Graells

引用次数: 2

A system-level design for foreground and background identification in 3D scenes 三维场景前景和背景识别的系统级设计

2016 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2016-05-22 DOI: 10.1109/ISCAS.2016.7539118

A. Safaei, Q. M. J. Wu

引用次数: 10

An efficient reference-based adaptive antenna impedance matching CMOS circuit 一种高效的基于参考的自适应天线阻抗匹配CMOS电路

2016 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2016-05-22 DOI: 10.1109/ISCAS.2016.7527512

A. Robichaud, F. Nabki, D. Deslandes

引用次数: 2

A wide dynamic range low power 2× time amplifier using current subtraction scheme 采用电流减法的宽动态范围低功率2倍时间放大器

2016 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2016-05-22 DOI: 10.1109/ISCAS.2016.7527277

H. Molaei, Ata Khorami, K. Hajsadeghi

引用次数: 4

A 14-bit differential-ramp single-slope column-level ADC for 640×512 uncooled infrared imager 用于640×512非制冷红外成像仪的14位微分斜坡单斜率柱级ADC

2016 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2016-05-22 DOI: 10.1109/ISCAS.2016.7538949

Dahe Liu, Wengao Lu, Zhongjian Chen, Yacong Zhang, Shuyu Lei, Guo Tan

引用次数: 10

Liquid state machine based pattern recognition on FPGA with firing-activity dependent power gating and approximate computing 基于射击活动相关功率门控和近似计算的FPGA模式识别

2016 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2016-05-22 DOI: 10.1109/ISCAS.2016.7527245

Qian Wang, Youjie Li, Peng Li

{"title":"Liquid state machine based pattern recognition on FPGA with firing-activity dependent power gating and approximate computing","authors":"Qian Wang, Youjie Li, Peng Li","doi":"10.1109/ISCAS.2016.7527245","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7527245","url":null,"abstract":"This paper presents an FPGA architecture and implementation of the Liquid State Machine, a spiking neural network model, for real world pattern recognition problems. The proposed architecture consists of a parallel digital reservoir with fixed synapses, and a readout stage that is tuned by a biologically plausible supervised learning rule. When evaluated using the TI46 speech corpus, a widely adopted speech recognition benchmark, the presented FPGA neuromorphic processors demonstrate highly competitive recognition performance and provide a runtime speedup of 88X over the 2.3 GHz AMD OpteronTM Processor. A number of critical design issues such as interconnection of liquid neurons, storage of synaptic weights and design of arithmetic blocks are addressed in this work. More importantly, it is shown that the unique computational structure and inherent resilience of the liquid state machine can be leveraged for highly efficient FPGA implementation. For t Iiis, it is demonstrated that the proposed firing-activity based power gating and approximate arithmetic computing with runtime adjustable precision can lead to up to 30.2% reduction in power and energy dissipation without greatly impacting speech recognition performance.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"2 1","pages":"361-364"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89244269","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 33

A temperature-independent PUF with a configurable duty cycle of CMOS ring oscillators 具有可配置的CMOS环形振荡器占空比的温度无关PUF

2016 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2016-05-22 DOI: 10.1109/ISCAS.2016.7539093

J. Agustin, M. López-Vallejo

引用次数: 11