2016 IEEE International Symposium on Circuits and Systems (ISCAS)最新文献

Global resource capacity algorithm with path splitting for virtual network embedding 基于路径分割的虚拟网络嵌入全局资源容量算法

2016 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2016-08-11 DOI: 10.1109/ISCAS.2016.7527328

Soroush Haeri, Qingye Ding, Zhida Li, L. Trajković

引用次数: 6

Live demonstration: An automatic evaluation platform for physical unclonable function test 现场演示:物理不可克隆功能测试的自动评估平台

2016 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2016-08-11 DOI: 10.1109/ISCAS.2016.7539068

Yijun Cui, Chenghua Wang, Weiqiang Liu, Máire O’Neill

引用次数: 1

Dynamic delay variation behaviour of RNS multiply-add architectures RNS乘加结构的动态延迟变化行为

2016 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2016-08-11 DOI: 10.1109/ISCAS.2016.7538963

Kleanthis Papachatzopoulos, I. Kouretas, Vassilis Paliouras

引用次数: 6

An effective generator-allocating method to enhance the robustness of power grid 提高电网鲁棒性的一种有效的发电机分配方法

2016 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2016-08-11 DOI: 10.1109/ISCAS.2016.7527330

Xi Zhang, Chi K. Tse

引用次数: 0

Low-cost configurable ring oscillator PUF with improved uniqueness 具有改进唯一性的低成本可配置环振荡器PUF

2016 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2016-08-11 DOI: 10.1109/ISCAS.2016.7527301

Yijun Cui, Chenghua Wang, Weiqiang Liu, Yifei Yu, Máire O’Neill, F. Lombardi

引用次数: 35

A passivity based stability measure for discrete 3-D IIR system realizations 基于无源性的离散三维IIR系统稳定性测度

2016 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2016-08-11 DOI: 10.1109/ISCAS.2016.7539096

J. Velten, A. Kummert, Daniel Wagner, K. Gałkowski

{"title":"A passivity based stability measure for discrete 3-D IIR system realizations","authors":"J. Velten, A. Kummert, Daniel Wagner, K. Gałkowski","doi":"10.1109/ISCAS.2016.7539096","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7539096","url":null,"abstract":"Increasing miniaturization of electronic systems and nano-technology enables more and more the realization of real time 3-D spatio-temporal signal processing and control systems. However, while stability is well understood for 1-D systems, open problems remain in the higher dimensional case, e.g. for 3D system realizations, especially with respect to computational complexity and thus hardware effort. We propose a basic and thus fast stability test for systems that can be given in a standard 3-D Roesser-like state space model. Most practical systems can be represented in that manner or at least be transformed into an equivalent system so that the test is applicable to most real world problems. The test itself is inspired by passivity assumptions which for example guarantee stability of electrical reactance networks. It represents a sufficient condition for stability and comprises eigenvalue computations of a sum of Gramian matrices of the same size as the system matrix, which leads in this step to the same complexity as a 1-D stability test. The latter can thus also be applied to adaptive systems, where the system matrix is periodically changing.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"97 1","pages":"2483-2486"},"PeriodicalIF":0.0,"publicationDate":"2016-08-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80624973","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Instantaneous pitch estimation of noisy speech signal with multivariate SST 基于多元海表温度的含噪语音信号瞬时基音估计

2016 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2016-05-22 DOI: 10.1109/ISCAS.2016.7527354

M. I. Molla, Mahboob Qaosar, K. Hirose

引用次数: 0

A 16-valued logic FPGA architecture employing analog memory circuit 采用模拟存储电路的16值逻辑FPGA结构

2016 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2016-05-22 DOI: 10.1109/ISCAS.2016.7527341

Renyuan Zhang, M. Kaneko

{"title":"A 16-valued logic FPGA architecture employing analog memory circuit","authors":"Renyuan Zhang, M. Kaneko","doi":"10.1109/ISCAS.2016.7527341","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7527341","url":null,"abstract":"A field programmable gate array (FPGA) architecture is developed in this work for implementing multi-valued logics (MVL). The arbitrary function of sixteen-valued logic, which is four-bit equivalent to conventional binary circuitry, can be carried out for approximate computations. The number of devices and interconnections in the proposed FPGA processor are both compacted in contrast to those of the conventional binary FPGAs. To memorize MVL datum statically, a self-refreshing and latch-up analog memory cell with four-bit accuracy is designed in a standard CMOS technology. Eighteen transistors are employed by this memory cell, which is only 37.5% of four sets of static binary memory cells. A 16-to-1 multiplexer is also proposed as the look-up table by using sixteen-valued logic signals for addressing A proof-of-concept FPGA processor is designed with 16 by 16 cell-array, and each cell has a four-bit-equivalent capacity. this manner, the number of transistors in lookup tables for such a scale is reduced to 29% of binary lookup tables. The circuit simulation results are presented for the approximate computations of linearly adding, subtracting, and Gaussian functions.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"51 1","pages":"718-721"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74152507","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Design of a power-efficient widely-programmable Gm-LC band-pass sigma-delta modulator for SDR 一种用于SDR的高效可编程Gm-LC带通σ - δ调制器的设计

2016 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2016-05-22 DOI: 10.1109/ISCAS.2016.7527168

A. Morgado, R. Fernández, J. M. Rosa

{"title":"Design of a power-efficient widely-programmable Gm-LC band-pass sigma-delta modulator for SDR","authors":"A. Morgado, R. Fernández, J. M. Rosa","doi":"10.1109/ISCAS.2016.7527168","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7527168","url":null,"abstract":"This paper presents the design and implementation of a fourth-order band-pass continuous-time ΣΔ modulator intended for the digitization of radio-frequency signals in software-defined-radio applications. The modulator architecture consists of two Gm-LC resonators with a tunable notch frequency and a 4-bit flash analog-to-digital converter in the forward path and a non-return-to-zero digital-to-analog converter with a finite-impulse-response filter in the feedback path. Both system-level and circuit-level reconfiguration techniques are included in order to allow the modulator to digitize signals placed at different carrier frequencies, from 450MHz to 950MHz. A proper synthesis methodology of the loop-filter coefficients at system level and the use of inverter-based switchable transconductors allow to optimize the performance in terms of robustness to circuit errors, stability and power consumption. The circuit, implemented in 65-nm CMOS, can digitise signals with up to 57-dB SNDR within a 40-MHz bandwidth, with an adaptive power dissipation of 16.7-to-22.8 mW and a programmable 1.2/2GHz clock rate1.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"58 1","pages":"53-56"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75409299","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Multi-bit flip-flop generation considering multi-corner multi-mode timing constraint 考虑多角多模时序约束的多比特触发器生成

2016 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2016-05-22 DOI: 10.1109/ISCAS.2016.7527357

Taehee Lee, JongWon Yi, Joon-Sung Yang

引用次数: 2