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Harnessing fabrication process signature for predicting yield across designs 利用制造过程特征来预测不同设计的良率
2016 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2016-05-22 DOI: 10.1109/ISCAS.2016.7527386
A. Ahmadi, H. Stratigopoulos, A. Nahar, Bob Orr, M. Pas, Y. Makris
{"title":"Harnessing fabrication process signature for predicting yield across designs","authors":"A. Ahmadi, H. Stratigopoulos, A. Nahar, Bob Orr, M. Pas, Y. Makris","doi":"10.1109/ISCAS.2016.7527386","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7527386","url":null,"abstract":"Yield estimation is an indispensable piece of information at the onset of high-volume manufacturing (HVM) of a device. The increasing demand for faster time-to-market and for designs with growing quality requirements and complexity, requires a quick and successful yield estimation prior to HVM. Prior to commencing HVM, a few early silicon wafers are typically produced and subjected to thorough characterization. One of the objectives of such characterization is yield estimation with better accuracy than what pre-silicon Monte Carlo simulation may offer. In this work, we propose predicting yield of a device using information from a similar previous-generation device, which is manufactured in the same technology node and in the same fabrication facility. For this purpose, we rely on the Bayesian Model Fusion (BMF) technique. The effectiveness of the proposed methodology is evaluated using sizable industrial data from two RF devices in a 65nm technology.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"182 1","pages":"898-901"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85068493","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A fully-digital spectrum shaping signaling for serial-data transceiver with crosstalk and ISI reduction property in multi-drop memory interfaces 一种用于串行数据收发器的全数字频谱整形信号，具有串扰和ISI减少特性
2016 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2016-05-22 DOI: 10.1109/ISCAS.2016.7539208
K. Gharibdoust, Gain Kim, A. Tajalli, Y. Leblebici
{"title":"A fully-digital spectrum shaping signaling for serial-data transceiver with crosstalk and ISI reduction property in multi-drop memory interfaces","authors":"K. Gharibdoust, Gain Kim, A. Tajalli, Y. Leblebici","doi":"10.1109/ISCAS.2016.7539208","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7539208","url":null,"abstract":"An efficient signaling scheme for serial-data transceivers (TRXs) has been proposed, which can properly reduce inter-symbol interference (ISI) and crosstalk (Xtalk) in memory interfaces. The proposed architecture relies on fully-digital implementation rather than analog/multi-tone approach, which can offer a very power-efficient and versatile silicon implementation. Moreover, the Xtalk induced noise can be fairly reduced by applying the proposed signaling, and the whole TRX can customize to the communication link trough digital calibration, while the aggregate data rate is kept fixed.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"12 1","pages":"2905-2905"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81619919","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Fault attack on FPGA implementations of Trivium stream cipher Trivium流密码FPGA实现中的故障攻击
2016 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2016-05-22 DOI: 10.1109/ISCAS.2016.7527302
F. E. Potestad-Ordóñez, C. Jiménez-Fernández, M. Valencia-Barrero
{"title":"Fault attack on FPGA implementations of Trivium stream cipher","authors":"F. E. Potestad-Ordóñez, C. Jiménez-Fernández, M. Valencia-Barrero","doi":"10.1109/ISCAS.2016.7527302","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7527302","url":null,"abstract":"This article presents the development of an experimental system to introduce faults in Trivium stream ciphers implemented on FPGA. The developed system has made possible to analyze the vulnerability of these implementations against fault attacks. The developed system consists of a mechanism that injects small pulses in the clock signal, and elements that analyze if a fault has been introduced, the number of faults introduced and its position in the inner state. The results obtained demonstrate the vulnerability of these implementations against fault attacks. As far as we know, this is the first time that experimental results of fault attack over Trivium are presented.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"31 1","pages":"562-565"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81911298","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
An efficient synthesis method for ternary reversible logic 一种有效的三元可逆逻辑综合方法
2016 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2016-05-22 DOI: 10.1109/ISCAS.2016.7539045
Saikat Basu, S. B. Mandal, A. Chakrabarti, S. Sur-Kolay
{"title":"An efficient synthesis method for ternary reversible logic","authors":"Saikat Basu, S. B. Mandal, A. Chakrabarti, S. Sur-Kolay","doi":"10.1109/ISCAS.2016.7539045","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7539045","url":null,"abstract":"While the role of ternary reversible and quantum computation has been growing, synthesis methodologies for such logic, have been addressed in only a few works. A reversible ternary logic function can be expressed as minterms by using projection operators. In this paper, a novel realization of the projection operators using a minimum number of permutative ternary Muthukrishnan-Stroud (M-S) gates is presented. Next, an efficient method for logic simplification for ternary reversible logic is proposed. This method along with the new construction of projection operators yields significantly lower gate cost of approximately 31% less than that obtained by earlier methodologies, for the synthesis of ternary benchmark circuits.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"24 1","pages":"2306-2309"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82129630","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Matrix reordering for efficient list sphere decoding of polar codes 矩阵重排序对极码的高效表球译码
2016 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2016-05-22 DOI: 10.1109/ISCAS.2016.7538902
Seyyed Ali Hashemi, C. Condo, W. Gross
{"title":"Matrix reordering for efficient list sphere decoding of polar codes","authors":"Seyyed Ali Hashemi, C. Condo, W. Gross","doi":"10.1109/ISCAS.2016.7538902","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7538902","url":null,"abstract":"The Successive-Cancellation List (SCL) algorithm is one of the best polar code decoding algorithms in terms of trade-offs between complexity and error correction performance. The List-Sphere Decoding (List-SD) algorithm has been recently proposed: it yields a better complexity/performance trade-off than SCL in the decoding of short polar codes, that can be used as component codes for larger polar codes. We exploit the structure of the generator matrix of polar codes to propose a matrix reordering technique which allows to significantly reduce the List-SD complexity without degrading its error correction performance, further improving the aforementioned trade-off. The proposed technique is implemented on hardware and it is shown that at the same Frame Error Rate (FER) and Bit Error Rate (BER), the matrix reordering can reduce the resource requirements of List-SD of up to 73%. Furthermore, FER and BER curves are plotted for case studies, showing that at the same complexity cost, matrix reordering improves the performance of List-SD of up to 0.75 dB at FER=10-2.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"90 1","pages":"1730-1733"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79507030","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A quasi-digital pressure/touch sensor prototype for orbital targets contact event monitoring 用于轨道目标接触事件监测的准数字压力/触摸传感器样机
2016 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2016-05-22 DOI: 10.1109/ISCAS.2016.7539185
Matteo Stoppa, P. Ros, M. Crepaldi, A. Chiolerio, D. Demarchi
{"title":"A quasi-digital pressure/touch sensor prototype for orbital targets contact event monitoring","authors":"Matteo Stoppa, P. Ros, M. Crepaldi, A. Chiolerio, D. Demarchi","doi":"10.1109/ISCAS.2016.7539185","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7539185","url":null,"abstract":"This paper presents a sensorized belt with four fully integrated pressure-touch sensors. We propose a very-low complexity sensor able to measure a pressure variation (up to 4 MPa) and to identify with accuracy a contact event at around 10 kPa. The overall pressure/touch sensor integrates a transducer, based on piezo capacitive material, coupled with a read-out circuit designed around a ring-oscillator. This converts the capacitance variation of the transducer into a quasi-digital signal characterized by a frequency range of 36.3-270 kHz with a very low standard deviation (2.3 kHz) and a sensitivity of 2.2 Hz/Pa. The tight integration of the electronics with the transducer results in a very compact all-in-one sensor system (overall size is 20 mm × 20 mm × 10 mm). Further, a major benefit of a low complexity design is the low power consumption, measured to be ~370 μW. Based on a quasi-digital approach (event-driven), the system is well suited for impulse-based wireless communication.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"25 1","pages":"2843-2846"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84168477","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
AFSEM: Advanced frequent subcircuit extraction method by graph mining approach for optimized cell library developments 先进的频繁子电路提取方法的图挖掘方法优化小区库的发展
2016 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2016-05-22 DOI: 10.1109/ISCAS.2016.7527327
Byung-Su Kim, H. Won, T. Han, Joon-Sung Yang
{"title":"AFSEM: Advanced frequent subcircuit extraction method by graph mining approach for optimized cell library developments","authors":"Byung-Su Kim, H. Won, T. Han, Joon-Sung Yang","doi":"10.1109/ISCAS.2016.7527327","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7527327","url":null,"abstract":"The optimization of cells and cell combinations used in design is critical to enhance the performance. If frequently used cell combinations are known in advance, a new cell development can be significantly optimized using the cell combinations for chip design. However, extracting frequent cell combinations is an NP hard problem. We propose a new framework, referring as AFSEM, to extract frequent cell combinations for design optimization. To solve this problem, we use a frequent subgraph mining method which is a process of discovering subgraphs. We present an advanced graph modeling and optimized frequent subgraph mining platform for a practical use. The experimental results with various designs demonstrate that the proposed method can discover various types of subcircuits for design optimization with various runtime optimization methods.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"14 1","pages":"662-665"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84734716","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Characterization of adhesive wafer bonded CMUTs realized from BCB based sealed cavity 基于BCB的密封腔实现的粘接晶圆键合CMUTs的表征
2016 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2016-05-22 DOI: 10.1109/ISCAS.2016.7539108
Rayyan Manwar, S. Chowdhury
{"title":"Characterization of adhesive wafer bonded CMUTs realized from BCB based sealed cavity","authors":"Rayyan Manwar, S. Chowdhury","doi":"10.1109/ISCAS.2016.7539108","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7539108","url":null,"abstract":"This paper presents the characterization results of a CMUT array fabricated using a Bisbenzocyclobutene (BCB) based adhesive wafer bonding technology. A resonant frequency of 17.3 MHz has been measured using an Agilent ENA5061B Vector Network Analyzer that is in good agreement with the results from 3-D FEA using IntelliSuite™. The extracted coupling coefficient from the electrical impedance measurement shows 40% higher transduction efficiency as compared to another research work published elsewhere. Optical measurements of the membrane deflection using a Polytec™ laser Doppler vibrometer and pitch catch mode experimental results validate the CMUT operation in both transmit and receive mode.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"23 1","pages":"2531-2534"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81710360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Towards free-breathing spirometery-on-chip: Design, implementation and preliminary experimental results 芯片上自由呼吸肺活量计:设计、实现和初步实验结果
2016 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2016-05-22 DOI: 10.1109/ISCAS.2016.7527435
E. Ghafar-Zadeh, Giancarlo Ayala-Charca, M. Matynia, S. Magierowski, Bahareh Gholamzadeh, M. Sawan
{"title":"Towards free-breathing spirometery-on-chip: Design, implementation and preliminary experimental results","authors":"E. Ghafar-Zadeh, Giancarlo Ayala-Charca, M. Matynia, S. Magierowski, Bahareh Gholamzadeh, M. Sawan","doi":"10.1109/ISCAS.2016.7527435","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7527435","url":null,"abstract":"This paper presents a new approach towards the development of a free-breathing micro-spirometer system on a single chip for point-of-care (POC) diagnosis of lung diseases. In this paper, we take the first step by designing and implementing a cantilever array chip using a standard micro-electromechanical system (MEMS) process. Each cantilever beam is incorporated with capacitive electrodes for sensing the cantilever deflection. Herein we also put forward a custom-made readout interface circuit for the measurement of minute capacitive changes and for data acquisition purposes. Furthermore, we demonstrate and discuss the fabrication and characterization and spirometry results. Based on these results, the device is used for measuring the breathing airflow with a resolution better than 12 bits. These preliminary results reveal the functionality and applicability of the propose d system for POC diagnostics applications related to lung disease.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"66 1","pages":"1094-1097"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83843118","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
An implantable wireless multi-channel neural prosthesis for epidural stimulation 一种用于硬膜外刺激的可植入无线多通道神经假体
2016 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2016-05-22 DOI: 10.1109/ISCAS.2016.7538975
D. Jiang, C. Eder, T. Perkins, A. Vanhoestenberghe, Matthew Schormans, Fangqi Liu, V. Valente, N. Donaldson, A. Demosthenous
{"title":"An implantable wireless multi-channel neural prosthesis for epidural stimulation","authors":"D. Jiang, C. Eder, T. Perkins, A. Vanhoestenberghe, Matthew Schormans, Fangqi Liu, V. Valente, N. Donaldson, A. Demosthenous","doi":"10.1109/ISCAS.2016.7538975","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7538975","url":null,"abstract":"This paper presents a fully implantable multi-channel neural prosthesis for epidural stimulation. The prosthesis features three telemetry-operated independent stimulators providing in total eighteen stimulation channels. The stimulator circuits were implemented in a 0.6-μm CMOS technology. The prosthesis is protected in a hermetically sealed ceramic enclosure and encapsulated in medical grade silicone rubber. In-vitro measured results with electrodes in saline are presented.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"74 1","pages":"2026-2029"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82609732","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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