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2016 IEEE International Symposium on Circuits and Systems (ISCAS)最新文献

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A new diffusion sparse RLS algorithm with improved convergence characteristics 一种改进收敛特性的扩散稀疏RLS算法
2016 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2016-05-22 DOI: 10.1109/ISCAS.2016.7539138
B. K. Das, M. Chakraborty
{"title":"A new diffusion sparse RLS algorithm with improved convergence characteristics","authors":"B. K. Das, M. Chakraborty","doi":"10.1109/ISCAS.2016.7539138","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7539138","url":null,"abstract":"A new sparsity aware recursive least squares (RLS) algorithm is proposed for distributed learning in a diffusion network. The algorithm deploys a RLS based adaptive filter at each node which is made sparsity aware by regularizing the conventional RLS cost function with a sparsity promoting penalty. The regularization introduces certain “zero-attracting” terms in the RLS update equation which help in shrinkage of the coefficients. Each node shares its tap weight information with every other node in its neighborhood and refines its own estimate by linearly combining the incoming tap weight information from neighboring nodes by a set of pre-defined weights. Results on both first and second order convergence of the algorithm are also provided. As simulations show, the proposed scheme outperforms other existing algorithms both in terms of convergence speed and steady state excess mean square error.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"22 1","pages":"2651-2654"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74421496","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Analog front end design for tags in backscatter-based tag-to-tag communication networks 基于反向散射的标签对标签通信网络中标签的模拟前端设计
2016 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2016-05-22 DOI: 10.1109/ISCAS.2016.7538982
A. Athalye, Jinghui Jian, Yasha Karimi, Samir R Das, P. Djurić
{"title":"Analog front end design for tags in backscatter-based tag-to-tag communication networks","authors":"A. Athalye, Jinghui Jian, Yasha Karimi, Samir R Das, P. Djurić","doi":"10.1109/ISCAS.2016.7538982","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7538982","url":null,"abstract":"Backscatter-based tag-to-tag communication (BBTT) is a paradigm wherein radio-less devices communicate with each other by using purely passive backscatter modulation. This allows for highly inexpensive and low power devices. Traditional backscattering devices like RFID tags are designed to communicate directly with an active reader leading to a centralized framework centered on the reader. Under a BBTT network, the tags talk to each other using backscattering in the presence of an external excitation signal, which can come from multiple sources (e.g., dedicated exciters, WiFi access points, TV towers, or cell phone towers). The two main components that determine the range and robustness of a passive tag-to-tag link are the power harvesting and demodulation circuit blocks in the analog front end (AFE). In this paper, we investigate the design constraints, optimization goals, and tradeoffs in the design of the AFE for BBTT tags. We first analyze the BBTT link theoretically and then verify the predicted optimal AFE parameters by simulations.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"36 1","pages":"2054-2057"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74522985","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Online malware defense using attack behavior model 基于攻击行为模型的在线恶意软件防御
2016 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2016-05-22 DOI: 10.1109/ISCAS.2016.7527492
Sanjeev Das, Hao Xiao, Yang Liu, Wei Zhang
{"title":"Online malware defense using attack behavior model","authors":"Sanjeev Das, Hao Xiao, Yang Liu, Wei Zhang","doi":"10.1109/ISCAS.2016.7527492","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7527492","url":null,"abstract":"Malware detection is one central topic in cybersecurity, which ideally requires an accurate, efficient and robust (to malware variants) solution. In this work, we propose a hardwareassisted architecture to perform online malware detection with two phases. In the offline phase, we learn the attack model of malware in the form of Deterministic Finite Automaton (DFA). During the runtime phase, we implement a DFA-based detection approach in hardware to check whether a program's execution contains the malicious behavior specified in the DFA. We evaluate our method using real world data of 168 Linux malware samples and 370 benign applications. The results show that our DFA-based approach can recognize malware variants of same family with the potential to detect zero-day attacks. Implemented in hardware, our architecture offers a real time detection with low performance and resource overhead, and more importantly, it cannot be bypassed by malware using sophisticated evasion techniques.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"10 1","pages":"1322-1325"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74906325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Design of CMOS telemetry circuits for in-vivo wireless sonomicrometry 活体无线声压测量CMOS遥测电路设计
2016 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2016-05-22 DOI: 10.1109/ISCAS.2016.7538974
Yarub Alazzawi, S. Chakrabartty
{"title":"Design of CMOS telemetry circuits for in-vivo wireless sonomicrometry","authors":"Yarub Alazzawi, S. Chakrabartty","doi":"10.1109/ISCAS.2016.7538974","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7538974","url":null,"abstract":"In this paper we present the design and implementation of CMOS telemetry circuits that can be used for in-vivo wireless sonomicrometry. The proposed transmitter circuit uses a digital pulse modulator that directly drives a sonomicrometry crystal using a train of ultra-wide-band pulses. The receiver is also designed using a pulse modulator which is configured to measure the energy of the ultrasonic pings received by the crystal. Using measured results from a prototype fabricated in a 0.5-μm CMOS process we verify the operation of the telemetry circuits and using 1mm diameter sonomicrometry crystals we present measurement results using three types of phantom setups: (a) a saline bath; (a) a chicken bone/bone-marrow; and (b)chicken breast and tissue. The measurement results demonstrate that for the three phantoms the integrated telemetry system can be used for bi-directional data transfer at a rate of 1 Kbps with a power dissipation of 611 μW.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"122 1","pages":"2022-2025"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75456868","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A novel autocorrelation-based timing mismatch C alibration strategy in Time-Interleaved ADCs 时间交错adc中一种新的基于自相关的时序失配C校准策略
2016 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2016-05-22 DOI: 10.1109/ISCAS.2016.7527540
Xiao Wang, Fule Li, Zhihua Wang
{"title":"A novel autocorrelation-based timing mismatch C alibration strategy in Time-Interleaved ADCs","authors":"Xiao Wang, Fule Li, Zhihua Wang","doi":"10.1109/ISCAS.2016.7527540","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7527540","url":null,"abstract":"This paper presents a novel autocorrelation-based strategy for timing mismatch calibration in Time-Interleaved ADCs. Different from common technique, the proposed strategy doesn't let autocorrelation between each channel and the reference channel converge to the peak, but to one of the channels with a certain time interval away from the reference channel. It can accelerate convergence. The interval can be selected with much freedom and easily implemented. Representation of sub-ADC output can be only one-bit without a “dead zone”, thus it can further reduce hardware overhead. It's also independent from offset and gain calibration. Using the proposed strategy in a 2-channel 14-bit 500MS/s TIADC, simulation shows a convergence time of 192ms to 0.1%oTs accuracy under 212.4MHz input and initial 5%oTs timing mismatch.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"124 1","pages":"1490-1493"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75501163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Ultra low voltage supply VCO with improved linearity 具有改进线性度的超低电压电源压控振荡器
2016 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2016-05-22 DOI: 10.1109/ISCAS.2016.7539070
Luís Henrique Rodovalho, H. Klimach, E. Fabris
{"title":"Ultra low voltage supply VCO with improved linearity","authors":"Luís Henrique Rodovalho, H. Klimach, E. Fabris","doi":"10.1109/ISCAS.2016.7539070","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7539070","url":null,"abstract":"In this paper, we present a VCO designed for operation at 250 mV dissipating 590 nW, free running frequency of 462 kHz with voltage-to-frequency maximum non-linearity of 0.33%. The VCO design aim to a time based ADC, whose resolution is highly limited by the non-linearity of the VCO itself, which may be corrected by further digital calibration. The proposed VCO uses a ring oscillator topology and employs forward body biasing to achieve high linearity in the analog domain.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"32 2","pages":"2379-2382"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72584537","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Low-complexity proportionate algorithms with sparsity-promoting penalties 具有稀疏性提升惩罚的低复杂度比例算法
2016 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2016-05-22 DOI: 10.1109/ISCAS.2016.7527218
T. Ferreira, Markus V. S. Lima, P. Diniz, W. Martins
{"title":"Low-complexity proportionate algorithms with sparsity-promoting penalties","authors":"T. Ferreira, Markus V. S. Lima, P. Diniz, W. Martins","doi":"10.1109/ISCAS.2016.7527218","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7527218","url":null,"abstract":"There are two main families of algorithms that tackle the problem of sparse system identification: the proportionate family and the one that employs sparsity-promoting penalty functions. Recently, a new approach was proposed with the l0-IPAPA algorithm, which combines proportionate updates with sparsity-promoting penalties. This paper proposes some modifications to the l0-IPAPA algorithm in order to decrease its computational complexity while preserving its good convergence properties. Among these modifications, the inclusion of a data-selection mechanism provides promising results. Some enlightening simulation results are provided in order to verify and compare the performance of the proposed algorithms.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"14 1","pages":"253-256"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74417654","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Efficient ILP-based variant-grid analog router 高效的基于ilp的变网格模拟路由器
2016 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2016-05-22 DOI: 10.1109/ISCAS.2016.7527478
Mohammad Torabi, Lihong Zhang
{"title":"Efficient ILP-based variant-grid analog router","authors":"Mohammad Torabi, Lihong Zhang","doi":"10.1109/ISCAS.2016.7527478","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7527478","url":null,"abstract":"As an indispensable portion in the modern system-on-chip designs, analog circuits are becoming more intractable and error prone in the time-consuming design process due to the nature of high parasitic sensitivity along with the shrinking design window in the advanced technology. Compared to the digital counterpart, analog circuits need to be designed more carefully taking into account special analog constraints besides the typical geometric requirements. Recent state-of-the-art analog routing research favors linear programming (LP) to satisfy various constraints, but leaving the routing efficiency as an open question. In this paper, we propose an integer linear programming (ILP) based algorithm to tackle the analog routing problem with a special focus on improving the routing efficiency. Hierarchical routing is developed to help the router to divide the entire routing area into multiple small regions, in each of which the ILP can derive a routing solution with speedy efficiency. Different from typical hierarchical methods, our proposed router deploys variant-grid resolution in different regions, that is, with a lower resolution for less crowded routing regions and a higher resolution for more congested regions. In this way, our proposed ILP-based router is much faster than any typical ones since it spends little time for the areas that do not need to be routed precisely. The experimental results show the high efficiency of our proposed method for both small circuits and especially big circuits without promising the routing quality.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"86 1","pages":"1266-1269"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75915878","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A high temperature wideband low noise amplifier for downhole applications 一种适用于井下的高温宽带低噪声放大器
2016 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2016-05-22 DOI: 10.1109/ISCAS.2016.7527396
Michael L. Cunningham, D. Ha, Kwang-Jin Koh
{"title":"A high temperature wideband low noise amplifier for downhole applications","authors":"Michael L. Cunningham, D. Ha, Kwang-Jin Koh","doi":"10.1109/ISCAS.2016.7527396","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7527396","url":null,"abstract":"As the oil industry continues to drill deeper to reach new wells, electronics are required to operate at extreme pressures and temperatures. Coupled with substantial real-time data targets, the need for robust high speed electronics is quickly on the rise. This paper presents a high temperature wideband low noise amplifier (LNA) with zero temperature coefficient maximum available gain (ZTCMAG) biasing for a downhole communication system. The proposed LNA is designed and prototyped using 0.25 μm GaN on SiC RF transistor technology, which is chosen due to the high junction temperature capability. Measurements show that the proposed LNA can operate reliably up to an ambient temperature of 230 C with a minimum noise figure (NF) of 2.0 dB, average gain of 16.1 dB, and input P1dB of 4.0 dBm from 230.5–285.5 MHz. The maximum variation with temperature from 25°C to 230°C is 1.53 dB for NF and 0.65 dB for gain.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"273 1","pages":"938-941"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75925689","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Stage-combined belief propagation decoding of polar codes 极性码的阶段组合信念传播译码
2016 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2016-05-22 DOI: 10.1109/ISCAS.2016.7527260
Jin Sha, Jun Lin, Zhongfeng Wang
{"title":"Stage-combined belief propagation decoding of polar codes","authors":"Jin Sha, Jun Lin, Zhongfeng Wang","doi":"10.1109/ISCAS.2016.7527260","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7527260","url":null,"abstract":"A novel modification is introduced in this paper for the belief propagation decoder of polar codes, wherein adjacent two processing stages are efficiently combined together to speed up decoding. Corresponding path based belief estimation method is presented in detail. The proposed decoder halves the number of stages of the conventional decoder and thus can significantly reduce the decoding latency and lower message memory requirement.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"9 1","pages":"421-424"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72672843","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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