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2016 IEEE International Symposium on Circuits and Systems (ISCAS)最新文献

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A low-noise closed-loop interface for high-G capacitive micro-accelerometer 高g电容式微加速度计的低噪声闭环接口
2016 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2016-05-22 DOI: 10.1109/ISCAS.2016.7539079
Meng Zhao, Zhongjian Chen, Yixin Yang, Yuze Niu, Guangyi Chen, Wengao Lu, Yacong Zhang
{"title":"A low-noise closed-loop interface for high-G capacitive micro-accelerometer","authors":"Meng Zhao, Zhongjian Chen, Yixin Yang, Yuze Niu, Guangyi Chen, Wengao Lu, Yacong Zhang","doi":"10.1109/ISCAS.2016.7539079","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7539079","url":null,"abstract":"A switched capacitor interface is presented in this paper for a ±50 g capacitive micro-accelerometer. In order to suppress the flicker noise of the frontend, a switched capacitor proportional-integral controller combined with a charge sensitive amplifier using correlated double sampling is proposed. The controller has a simple structure with minimized number of switches and cancels the offset of both the charge sensitive amplifier and itself. A delay buffer following the controller is used to generate a z-1/2 delay and drive the middle plate of the sensing element. The interface is implemented in a 0.35 μm 3.3 V/15 V CMOS process and the area of the chip is 11.75 mm2. The fabricated prototype circuit operates under 15 V and 3.3 V supply at a sampling clock of 100 kHz. Meanwhile, a sensitivity of 99.7 mV/g is achieved with the bias instability of 200 μg. The dynamic range of the accelerometer is 106.16 dB over a signal bandwidth of 200 Hz.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"88 1","pages":"2415-2418"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74934048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
FPGA design of approximate semidefinite relaxation for data detection in large MIMO wireless systems 大型MIMO无线系统中数据检测的近似半定松弛FPGA设计
2016 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2016-05-22 DOI: 10.1109/ISCAS.2016.7539140
Oscar Castañeda, T. Goldstein, Christoph Studer
{"title":"FPGA design of approximate semidefinite relaxation for data detection in large MIMO wireless systems","authors":"Oscar Castañeda, T. Goldstein, Christoph Studer","doi":"10.1109/ISCAS.2016.7539140","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7539140","url":null,"abstract":"We propose a novel, near-optimal data detection algorithm and a corresponding FPGA design for large multiple-input multiple-output (MIMO) wireless systems. Our algorithm, referred to as TASER (short for triangular approximate semidefinite relaxation), relaxes the maximum-likelihood (ML) detection problem to a semidefinite program and solves a non-convex approximation using a preconditioned forward-backward splitting procedure. We show that TASER achieves near-ML performance at low computational complexity, even for large-dimensional MIMO systems. We develop a systolic array that implements TASER and achieves high throughput at low hardware complexity. To demonstrate the effectiveness of our solution, we develop reference designs on a Xilinx Virtex-7 FPGA for various antenna configurations. One of our TASER designs achieves up to 98 Mb/s for a 32-user system that employs QPSK, while consuming only 150 k FPGA look-up tables.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"70 1","pages":"2659-2662"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77391616","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A novel low-power and high-speed dual-modulus prescaler based on extended true single-phase clock logic 一种基于扩展真单相时钟逻辑的新型低功耗高速双模预分频器
2016 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2016-05-22 DOI: 10.1109/ISCAS.2016.7539162
S. Jia, Ziyi Wang, Zijin Li, Yuan Wang
{"title":"A novel low-power and high-speed dual-modulus prescaler based on extended true single-phase clock logic","authors":"S. Jia, Ziyi Wang, Zijin Li, Yuan Wang","doi":"10.1109/ISCAS.2016.7539162","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7539162","url":null,"abstract":"A novel low-power and high-speed dual-modulus prescaler based on extended true single-phase clock (E-TSPC) scheme is presented. By restricting the short-circuit current in noncritical branchs, the design reduces the major source of power dissipation in E-TSPC scheme. The presented design enhances the maximum working frequency with shorter critical path and lower load capacitances. Simulation results in SMIC 40nm process show that compared with referenced E-TSPC based designs at least 61.2% (divide-by-2) and 41.1% (divide-by-3) reduction in power delay product (PDP) can be achieved by the proposed design.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"140 1","pages":"2751-2754"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77656358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
STT-MRAM write energy minimization via area optimization under dynamic voltage Scaling STT-MRAM在动态电压缩放下通过面积优化实现写入能量最小化
2016 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2016-05-22 DOI: 10.1109/ISCAS.2016.7539172
Kien Trinh Quang, S. Ruocco, M. Alioto
{"title":"STT-MRAM write energy minimization via area optimization under dynamic voltage Scaling","authors":"Kien Trinh Quang, S. Ruocco, M. Alioto","doi":"10.1109/ISCAS.2016.7539172","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7539172","url":null,"abstract":"In this paper we show that the area optimization of STT-MRAM bitcells can deliver a substantial reduction in the energy per write access when dynamic voltage scaling (DVS) is adopted. Indeed, the increase in the bitcell area enables the reduction in the write energy consumed by the bitcells at the expense of the energy of peripheral circuits, when lowering the supply voltage. The proposed approach addresses a fundamental challenge in STT-MRAM arrays, whose energy efficiency is well-known to be severely degraded by the large energy cost of write. Simulations of STT-MRAM arrays built with four widely adopted bitcells showed that up to 2.5X write energy reduction and 5X performance improvement are obtained at 2X bitcell area cost at 0.7 V, compared to minimum-sized bitcell.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"15 1","pages":"2791-2794"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80051994","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A process compensated gain cell embedded-DRAM for ultra-low-power variation-aware design 超低功耗变化感知设计的过程补偿增益单元嵌入式dram
2016 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2016-05-22 DOI: 10.1109/ISCAS.2016.7527413
R. Giterman, A. Teman, P. Meinerzhagen, A. Fish, A. Burg
{"title":"A process compensated gain cell embedded-DRAM for ultra-low-power variation-aware design","authors":"R. Giterman, A. Teman, P. Meinerzhagen, A. Fish, A. Burg","doi":"10.1109/ISCAS.2016.7527413","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7527413","url":null,"abstract":"Gain cell embedded DRAM (GC-eDRAM) is a high-density alternative to SRAM for ultra-low-power systems. However, due to its dynamic nature, GC-eDRAM requires power-hungry refresh cycles to ensure data retention. Traditional design approaches dictate configuration of the refresh rate according to the worst bitcell, when biased at low-probability, worst-case conditions. However, due to the process variations and local mismatch that can significantly deteriorate the data retention time of a GC-eDRAM bitcell, this design approach often leads to a large power overhead. In this paper, we present a novel GC-eDRAM architecture, incorporating several techniques for variation-aware operation. The primary feature of this architecture is an improved replica scheme for process compensated access tracking that enables calibration for process variations and adaptive refresh according to the array access statistics. The array is shown to ensure data integrity, providing as much as a 7x reduction in retention power over worst-case refresh-rate design for 20% write activity.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"224 1","pages":"1006-1009"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80052547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Enabling quasi-adiabatic logic arrays for silicon and beyond-silicon technologies 为硅和超硅技术实现准绝热逻辑阵列
2016 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2016-05-22 DOI: 10.1109/ISCAS.2016.7539200
V. Tenace, A. Calimera, E. Macii, M. Poncino
{"title":"Enabling quasi-adiabatic logic arrays for silicon and beyond-silicon technologies","authors":"V. Tenace, A. Calimera, E. Macii, M. Poncino","doi":"10.1109/ISCAS.2016.7539200","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7539200","url":null,"abstract":"Adiabatic logic aims at mimicking an adiabatic (i.e., without energy exchange) charging process in digital circuits. Although regarded as a mostly theoretical computation style, research on the topic has been constantly active over the years, providing several demonstrations of working implementations [1]. The interest in adiabatic circuits recently increased with the introduction of emerging devices, e.g., Nanoelectromechanicals switches (NEMs) [2] and graphene p-n junctions [3], which have been proven to be good technological vehicles for adiabatic computing. Despite their energy efficiency, adiabatic logic faced severe limitations in reaching large scale integration due to the difficulty in logic pipelining and the lack of CAD tools able to cope with today's design complexity.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"45 1","pages":"2897-2897"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79034654","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Towards efficient polynomial multiplication for lattice-based cryptography 基于格密码的高效多项式乘法研究
2016 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2016-05-22 DOI: 10.1109/ISCAS.2016.7527456
Chaohui Du, Guoqiang Bai
{"title":"Towards efficient polynomial multiplication for lattice-based cryptography","authors":"Chaohui Du, Guoqiang Bai","doi":"10.1109/ISCAS.2016.7527456","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7527456","url":null,"abstract":"Ring learning with errors (Ring-LWE) is the basis of various lattice based cryptosystems. The most critical and computationally intensive operation of Ring-LWE based cryptosystems is polynomial multiplication over rings. In this paper, we introduce several optimization techniques to build an efficient polynomial multiplier with the number theoretic transform (NTT). We propose a technique to optimize the bit-reverse operation of NTT and inverse-NTT. With additional optimizations, our polynomial multiplier reduces the required clock cycles from (8n+1.5n lg n) to (2n+1.5n lg n). By exploiting the relationship of the constant factors, our polynomial multiplier is able to reduce the number of constant factors from 4n to 2.5n, which saves about 37.5% ROM storage. In addition, we propose a novel memory access scheme to achieve maximum utilization of the butterfly operator. With these techniques, our polynomial multiplier is capable to perform 57304/26913 polynomial multiplications per second for dimension 256/512 on a Spartan-6 FPGA.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"289 1","pages":"1178-1181"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79434405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
A new countermeasure against scan-based side-channel attacks 一种新的对抗扫描侧信道攻击的方法
2016 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2016-05-22 DOI: 10.1109/ISCAS.2016.7538900
Yanhui Luo, Aijiao Cui, G. Qu, Huawei Li
{"title":"A new countermeasure against scan-based side-channel attacks","authors":"Yanhui Luo, Aijiao Cui, G. Qu, Huawei Li","doi":"10.1109/ISCAS.2016.7538900","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7538900","url":null,"abstract":"Scan design has been widely used to facilitate the testing of integrated circuits (ICs). However, it also provides attackers a side-channel to access the internal states of crypto chips and thus becomes a great threat to the security of the cipher keys. We propose a secure scan design scheme to protect crypto chips against such scan-based side-channel attacks. In this scheme, we introduce a shift register to control the working mode of certain scan cells. Only when the user configures the shift register correctly, can the scan design work normally under testing mode. We show that the proposed secure scan design can effectively resist the existing scan-based attacks. We also demonstrate that this approach has low area overhead while maintaining the testability of original design.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"24 1","pages":"1722-1725"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81813639","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
A bidirectional neural interface IC with high voltage compliance and spectral separation 一种具有高电压顺应性和频谱分离性的双向神经接口集成电路
2016 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2016-05-22 DOI: 10.1109/ISCAS.2016.7539160
Michael Haas, U. Bihr, J. Anders, M. Ortmanns
{"title":"A bidirectional neural interface IC with high voltage compliance and spectral separation","authors":"Michael Haas, U. Bihr, J. Anders, M. Ortmanns","doi":"10.1109/ISCAS.2016.7539160","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7539160","url":null,"abstract":"This paper presents a fully integrated, bidirectional, neural interface, which is composed of a high voltage (HV) stimulator and a low voltage (LV) neural front-end with active, spectral separation. The stimulator uses a supply of ±9V in order to achieve a high voltage compliance (VC), whereas the recorder has a supply voltage of 3 V for high power efficiency. By using a HV transistor to separate the two parts, a safe operation of stimulator and recorder with different supply voltages can be guaranteed. Thereby the presented architecture can deliver a maximum stimulation current of ±10mA with a dynamic range of 50 dB and a VC of ±8.2 V. The implemented recording part consumes 52 μW and achieves a simulated input referred noise of 2.5μVrms in the low frequency band from 0.1 Hz to 200 Hz and 3.1 μVrms in the high frequency band from 200 Hz to 7.5 kHz. The combined recorder/stimulator requires 0.378 mm2 per channel. A prototype of the interface has been implemented and manufactured in a standard 0.18 μm HV CMOS technology.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"53 1","pages":"2743-2746"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85627192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Miniaturized UWB offset power divider with reflection cancellation and enhanced isolation 具有反射抵消和增强隔离的小型化UWB偏置功率分配器
2016 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2016-05-22 DOI: 10.1109/ISCAS.2016.7527202
A. Sayed, H. Ahmed, Ayman M. ElTager
{"title":"Miniaturized UWB offset power divider with reflection cancellation and enhanced isolation","authors":"A. Sayed, H. Ahmed, Ayman M. ElTager","doi":"10.1109/ISCAS.2016.7527202","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7527202","url":null,"abstract":"In this paper, a miniaturized, ultra-wideband, dual-section, two-way offset power divider, covering the frequency range from 0.6 to 6 GHz, with reflection cancellation and enhanced isolation, is presented. The divider small form factor is achieved through the use of a π-structure that replaces the λ/4 transmission lines in each of the divider's sections. The dimensions of the open stubs forming this structure are adjusted so as to present minimum reflection at twice the design frequency; this, together with using two-transformer sections, serve to obtain the divider ultra-wideband operation despite using a two-way offset structure only. The implemented design provides an average insertion loss of 0.4 dB, an average isolation of 18 dB and an output return loss of better than 12 dB throughout the whole operation bandwidth 0.6–6 GHz, (a fractional bandwidth of approximately 164%). To the authors' knowledge, this is the widest achieved bandwidth using merely a two-way offset divider with reflection cancellation performance.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"53 1","pages":"189-192"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85915343","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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