Enabling quasi-adiabatic logic arrays for silicon and beyond-silicon technologies

Abstract

Adiabatic logic aims at mimicking an adiabatic (i.e., without energy exchange) charging process in digital circuits. Although regarded as a mostly theoretical computation style, research on the topic has been constantly active over the years, providing several demonstrations of working implementations [1]. The interest in adiabatic circuits recently increased with the introduction of emerging devices, e.g., Nanoelectromechanicals switches (NEMs) [2] and graphene p-n junctions [3], which have been proven to be good technological vehicles for adiabatic computing. Despite their energy efficiency, adiabatic logic faced severe limitations in reaching large scale integration due to the difficulty in logic pipelining and the lack of CAD tools able to cope with today's design complexity.