{"title":"高g电容式微加速度计的低噪声闭环接口","authors":"Meng Zhao, Zhongjian Chen, Yixin Yang, Yuze Niu, Guangyi Chen, Wengao Lu, Yacong Zhang","doi":"10.1109/ISCAS.2016.7539079","DOIUrl":null,"url":null,"abstract":"A switched capacitor interface is presented in this paper for a ±50 g capacitive micro-accelerometer. In order to suppress the flicker noise of the frontend, a switched capacitor proportional-integral controller combined with a charge sensitive amplifier using correlated double sampling is proposed. The controller has a simple structure with minimized number of switches and cancels the offset of both the charge sensitive amplifier and itself. A delay buffer following the controller is used to generate a z-1/2 delay and drive the middle plate of the sensing element. The interface is implemented in a 0.35 μm 3.3 V/15 V CMOS process and the area of the chip is 11.75 mm2. The fabricated prototype circuit operates under 15 V and 3.3 V supply at a sampling clock of 100 kHz. Meanwhile, a sensitivity of 99.7 mV/g is achieved with the bias instability of 200 μg. The dynamic range of the accelerometer is 106.16 dB over a signal bandwidth of 200 Hz.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"88 1","pages":"2415-2418"},"PeriodicalIF":0.0000,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A low-noise closed-loop interface for high-G capacitive micro-accelerometer\",\"authors\":\"Meng Zhao, Zhongjian Chen, Yixin Yang, Yuze Niu, Guangyi Chen, Wengao Lu, Yacong Zhang\",\"doi\":\"10.1109/ISCAS.2016.7539079\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A switched capacitor interface is presented in this paper for a ±50 g capacitive micro-accelerometer. In order to suppress the flicker noise of the frontend, a switched capacitor proportional-integral controller combined with a charge sensitive amplifier using correlated double sampling is proposed. The controller has a simple structure with minimized number of switches and cancels the offset of both the charge sensitive amplifier and itself. A delay buffer following the controller is used to generate a z-1/2 delay and drive the middle plate of the sensing element. The interface is implemented in a 0.35 μm 3.3 V/15 V CMOS process and the area of the chip is 11.75 mm2. The fabricated prototype circuit operates under 15 V and 3.3 V supply at a sampling clock of 100 kHz. Meanwhile, a sensitivity of 99.7 mV/g is achieved with the bias instability of 200 μg. The dynamic range of the accelerometer is 106.16 dB over a signal bandwidth of 200 Hz.\",\"PeriodicalId\":6546,\"journal\":{\"name\":\"2016 IEEE International Symposium on Circuits and Systems (ISCAS)\",\"volume\":\"88 1\",\"pages\":\"2415-2418\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-05-22\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 IEEE International Symposium on Circuits and Systems (ISCAS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISCAS.2016.7539079\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISCAS.2016.7539079","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A low-noise closed-loop interface for high-G capacitive micro-accelerometer
A switched capacitor interface is presented in this paper for a ±50 g capacitive micro-accelerometer. In order to suppress the flicker noise of the frontend, a switched capacitor proportional-integral controller combined with a charge sensitive amplifier using correlated double sampling is proposed. The controller has a simple structure with minimized number of switches and cancels the offset of both the charge sensitive amplifier and itself. A delay buffer following the controller is used to generate a z-1/2 delay and drive the middle plate of the sensing element. The interface is implemented in a 0.35 μm 3.3 V/15 V CMOS process and the area of the chip is 11.75 mm2. The fabricated prototype circuit operates under 15 V and 3.3 V supply at a sampling clock of 100 kHz. Meanwhile, a sensitivity of 99.7 mV/g is achieved with the bias instability of 200 μg. The dynamic range of the accelerometer is 106.16 dB over a signal bandwidth of 200 Hz.