{"title":"时间交错adc中一种新的基于自相关的时序失配C校准策略","authors":"Xiao Wang, Fule Li, Zhihua Wang","doi":"10.1109/ISCAS.2016.7527540","DOIUrl":null,"url":null,"abstract":"This paper presents a novel autocorrelation-based strategy for timing mismatch calibration in Time-Interleaved ADCs. Different from common technique, the proposed strategy doesn't let autocorrelation between each channel and the reference channel converge to the peak, but to one of the channels with a certain time interval away from the reference channel. It can accelerate convergence. The interval can be selected with much freedom and easily implemented. Representation of sub-ADC output can be only one-bit without a “dead zone”, thus it can further reduce hardware overhead. It's also independent from offset and gain calibration. Using the proposed strategy in a 2-channel 14-bit 500MS/s TIADC, simulation shows a convergence time of 192ms to 0.1%oTs accuracy under 212.4MHz input and initial 5%oTs timing mismatch.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"124 1","pages":"1490-1493"},"PeriodicalIF":0.0000,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":"{\"title\":\"A novel autocorrelation-based timing mismatch C alibration strategy in Time-Interleaved ADCs\",\"authors\":\"Xiao Wang, Fule Li, Zhihua Wang\",\"doi\":\"10.1109/ISCAS.2016.7527540\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a novel autocorrelation-based strategy for timing mismatch calibration in Time-Interleaved ADCs. Different from common technique, the proposed strategy doesn't let autocorrelation between each channel and the reference channel converge to the peak, but to one of the channels with a certain time interval away from the reference channel. It can accelerate convergence. The interval can be selected with much freedom and easily implemented. Representation of sub-ADC output can be only one-bit without a “dead zone”, thus it can further reduce hardware overhead. It's also independent from offset and gain calibration. Using the proposed strategy in a 2-channel 14-bit 500MS/s TIADC, simulation shows a convergence time of 192ms to 0.1%oTs accuracy under 212.4MHz input and initial 5%oTs timing mismatch.\",\"PeriodicalId\":6546,\"journal\":{\"name\":\"2016 IEEE International Symposium on Circuits and Systems (ISCAS)\",\"volume\":\"124 1\",\"pages\":\"1490-1493\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-05-22\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"9\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 IEEE International Symposium on Circuits and Systems (ISCAS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISCAS.2016.7527540\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISCAS.2016.7527540","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A novel autocorrelation-based timing mismatch C alibration strategy in Time-Interleaved ADCs
This paper presents a novel autocorrelation-based strategy for timing mismatch calibration in Time-Interleaved ADCs. Different from common technique, the proposed strategy doesn't let autocorrelation between each channel and the reference channel converge to the peak, but to one of the channels with a certain time interval away from the reference channel. It can accelerate convergence. The interval can be selected with much freedom and easily implemented. Representation of sub-ADC output can be only one-bit without a “dead zone”, thus it can further reduce hardware overhead. It's also independent from offset and gain calibration. Using the proposed strategy in a 2-channel 14-bit 500MS/s TIADC, simulation shows a convergence time of 192ms to 0.1%oTs accuracy under 212.4MHz input and initial 5%oTs timing mismatch.