Efficient ILP-based variant-grid analog router

As an indispensable portion in the modern system-on-chip designs, analog circuits are becoming more intractable and error prone in the time-consuming design process due to the nature of high parasitic sensitivity along with the shrinking design window in the advanced technology. Compared to the digital counterpart, analog circuits need to be designed more carefully taking into account special analog constraints besides the typical geometric requirements. Recent state-of-the-art analog routing research favors linear programming (LP) to satisfy various constraints, but leaving the routing efficiency as an open question. In this paper, we propose an integer linear programming (ILP) based algorithm to tackle the analog routing problem with a special focus on improving the routing efficiency. Hierarchical routing is developed to help the router to divide the entire routing area into multiple small regions, in each of which the ILP can derive a routing solution with speedy efficiency. Different from typical hierarchical methods, our proposed router deploys variant-grid resolution in different regions, that is, with a lower resolution for less crowded routing regions and a higher resolution for more congested regions. In this way, our proposed ILP-based router is much faster than any typical ones since it spends little time for the areas that do not need to be routed precisely. The experimental results show the high efficiency of our proposed method for both small circuits and especially big circuits without promising the routing quality.