2016 IEEE International Symposium on Circuits and Systems (ISCAS)最新文献_第7页

High performance low overhead template-based Cell-Interleave Pipeline (TCIP) for asynchronous-logic QDI circuits 异步逻辑QDI电路中基于模板的高性能低开销Cell-Interleave Pipeline (TCIP)

2016 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2016-05-22 DOI: 10.1109/ISCAS.2016.7538909

Weng-Geng Ho, Nan Liu, K. Z. L. Ne, Kwen-Siong Chong, B. Gwee, J. Chang

{"title":"High performance low overhead template-based Cell-Interleave Pipeline (TCIP) for asynchronous-logic QDI circuits","authors":"Weng-Geng Ho, Nan Liu, K. Z. L. Ne, Kwen-Siong Chong, B. Gwee, J. Chang","doi":"10.1109/ISCAS.2016.7538909","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7538909","url":null,"abstract":"We propose a novel Template-based Cell-Interleave Pipeline (TCIP) approach for generating high performance and yet low overhead asynchronous-logic (async) quasi-delay-insensitive (QDI) circuits. Our TCIP approach exploits the characteristics of the four prevalent QDI cell templates, namely Weak-Conditioned Half-Buffer (WCHB), Pre-Charged HalfBuffer (PCHB), Autonomous Signal-Validity Half-Buffer (ASVHB), and Sense-Amplifier Half-Buffer (SAHB), and then strategically interleave these template cells to form a composite pipeline. There are three main features in our TCIP approach. First, all QDI cell templates are first standardized with the same interface signals, and their corresponding cells are characterized in terms of transistor count, cycle time and energy dissipation for ease of comparison/selection/replacement. Second, our TCIP approach prioritizes the speed requirement when forming the initial pipeline circuits, and then subsequently reduces circuit overheads by interleaving various template cells without compromising the speed significantly. Third, the final optimized QDI pipeline circuit inherently features high robustness against process-voltage-temperature (PVT) variations, hence suitable for dynamic-voltage-scaling (DVS) operation. By means of 65nm CMOS process, we demonstrate a 4-bit pipeline tree adder based on the proposed TCIP approach, and benchmark it against the WCHB, PCHB, ASVHB and SAHB counterparts. These five designs feature same high operational robustness, nonetheless the design based on our TCIP approach is more competitive. Particularly, the designs based on reported approaches are, on average, ~1.22× more transistor count, ~1.21× slower and ~1.22× higher energy dissipation. Furthermore, under DVS operation from 1.2V to 0.3V, our proposed TCIP adder can reduce up to 88% energy for non-speed critical applications.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"34 1","pages":"1762-1765"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91234674","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Hierarchical temporal dependent rate-distortion optimization for low-delay coding 低延迟编码的分层时间相关率失真优化

2016 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2016-05-22 DOI: 10.1109/ISCAS.2016.7527304

Yanbo Gao, Ce Zhu, Shuai Li

{"title":"Hierarchical temporal dependent rate-distortion optimization for low-delay coding","authors":"Yanbo Gao, Ce Zhu, Shuai Li","doi":"10.1109/ISCAS.2016.7527304","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7527304","url":null,"abstract":"Hierarchical coding structure (HCS) is one of the most important components in High Efficiency Video Coding (HEVC) that improves the coding performance greatly, especially for Low-Delay (LD) coding. It groups frames into different layers and enc odes them with different quantization parameters (QP) and different reference mechanisms. Due to the extensively used inter-prediction, the coding of frames in different layers is highly dependent and an appropriate QP and reference selection scheme may significantly improve the performance by taking advantage of such temporal dependency. However in the current HEVC codec, a predefined HCS, such as the Low-Delay HCS (LD-HCS), is performed without considering the different characteristic of different video contents, thus leading to a suboptimal coding solution. In this paper, the hierarchical temporal relationship under LD-HCS is first investigated and a hierarchical temporal propagation chain is constructed to describe the temporal dependency among frames. Then a hierarchical temporal dependent rate-distortion optimization scheme is developed specifically for the LD-HCS in HEVC. Experiments results show that the proposed scheme achieves BD-rate saving of 2.9% and 2.8% in average against HEVC codec under LD-HCS of P and B frames, respectively, with a negligible increase in encoding time.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"37 1","pages":"570-573"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91292392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Small-signal analysis of closed-loop PWM boost converter in CCM with complex impedance load 复杂阻抗负载下CCM闭环PWM升压变换器的小信号分析

2016 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2016-05-22 DOI: 10.1109/ISCAS.2016.7527263

Dalvir K. Saini, A. Ayachit, M. Kazimierczuk, H. Sekiya

引用次数: 8

Modelling and characterization of dynamic behavior of coupled memristor circuits 耦合忆阻电路动态特性的建模与表征

2016 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2016-05-22 DOI: 10.1109/ISCAS.2016.7527334

J. Eshraghian, H. Iu, T. Fernando, Dongsheng Yu, Zhen Li

引用次数: 17

Autonomous smartwatch with flexible sensors for accurate and continuous mapping of skin temperature 带有柔性传感器的自动智能手表，可准确连续地绘制皮肤温度图

2016 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2016-05-22 DOI: 10.1109/ISCAS.2016.7527239

M. Magno, G. Salvatore, S. Mutter, Waleed Farrukh, G. Tröster, L. Benini

{"title":"Autonomous smartwatch with flexible sensors for accurate and continuous mapping of skin temperature","authors":"M. Magno, G. Salvatore, S. Mutter, Waleed Farrukh, G. Tröster, L. Benini","doi":"10.1109/ISCAS.2016.7527239","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7527239","url":null,"abstract":"Epidermal sensors, which form an intimate and robust contact with the skin, are capable of providing clinically relevant information about cardiovascular health, electrophysiology and dermatology with high accuracy and in an unobtrusive manner. To enable clinical applications, however, continuous and long-term monitoring is necessary. In addition, wireless and energetically autonomous systems are highly desirable to eliminate the needs of tethers and cables for powering and data transmission. Such requirements call for devices that combine accurate and precise sensing with high performance electronics for signal treatment, communication and power management in formats which conformal laminate on the body. In this work, we present a novel system whose design leverages on the recent developments in low power wearable devices and flexible sensors. It consists of an ultra-low power smartwatch connected to flexible solar modules assembled on a strap and an array of epidermal temperature sensors which are mounted on the wrist. Preliminary experiments show how this platform is well-suited for long-term, accurate and continuous mapping of the temperature of the skin.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"38 1","pages":"337-340"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88486950","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

Generating voltage drop aware current budgets for RC power grids 基于电压降感知的直流电网电流预算

2016 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2016-05-22 DOI: 10.1109/ISCAS.2016.7539121

Zahi Moudallal, F. Najm

引用次数: 0

Cyclical sensing integrate-and-fire circuit for memristor array based neuromorphic computing 基于记忆电阻器阵列的神经形态计算循环传感集火电路

2016 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2016-05-22 DOI: 10.1109/ISCAS.2016.7527394

Hao Jiang, Weijie Zhu, Fu Luo, Kangjun Bai, Chenchen Liu, Xiaorong Zhang, J. Yang, Q. Xia, Yiran Chen, Qing Wu

{"title":"Cyclical sensing integrate-and-fire circuit for memristor array based neuromorphic computing","authors":"Hao Jiang, Weijie Zhu, Fu Luo, Kangjun Bai, Chenchen Liu, Xiaorong Zhang, J. Yang, Q. Xia, Yiran Chen, Qing Wu","doi":"10.1109/ISCAS.2016.7527394","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7527394","url":null,"abstract":"The brain-inspired, spike-based neuromorphic system is highly anticipated in the artificial intelligence community due to its high computational efficiency. The recently developed memristor-crossbar-array technology, which is able to efficiently emulate the plasticity of biological synapses and accommodate matrix multiplication, has demonstrated its potential for neuromorphic computing. To facilitate the computation, a high-speed integrate-and-fire circuit (IFC) and a counter were previously developed to efficiently convert the current from the memristor array into rate-coded spikes. However, the linear dynamic range of the circuit, which is limited by its responding speed, is challenged when the input intensity and the conductance of the memristor array are both high simultaneously. In this paper, a novel cyclical sensing scheme is developed that can significantly extend the linear dynamic range of the original IFC. Meanwhile, the power efficiency of the IFC can also be increased. The circuit simulation results indicated that the cyclical sensing IFC was able to efficiently and accurately facilitate the matrix multiplication when it was integrated with a 32×32 memristor crossbar array. With the optimized crossbar array structure and its peripheral circuits, the developed cyclical sensing IFC has shown great promise in accelerating matrix multiplication in spike-based computing systems.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"1 1","pages":"930-933"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76838041","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

Device modelling of bendable MOS transistors 可弯曲MOS晶体管的器件建模

2016 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2016-05-22 DOI: 10.1109/ISCAS.2016.7527501

H. Heidari, W. Navaraj, G. Toldi, R. Dahiya

引用次数: 5

A pipeline ADC for very high conversion rates 一个流水线ADC非常高的转换率

2016 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2016-05-22 DOI: 10.1109/ISCAS.2016.7527529

D. Muratore, E. Bonizzoni, F. Maloberti

引用次数: 4

Verilog-a modeling of Silicon Photo-Multipliers verilog -硅光电倍增器的模型

2016 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2016-05-22 DOI: 10.1109/ISCAS.2016.7527479

G. Giustolisi, G. Palumbo, P. Finocchiaro, A. Pappalardo

引用次数: 2