A power efficient PLL with in-loop-bandwidth spread-spectrum modulation scheme using a charge-based discrete-time loop filter

This paper presents an in-loop-bandwidth spread-spectrum clock generation by proposing a linear charge-based discrete-time loop filter. The proposed architecture achieves a power efficient (2.29mA/GHz) spread-spectrum modulation scheme based upon a conventional CP-PLL. This work supports a modulation range of +/−2.7 % of a 700 MHz output frequency with the modulation rate in the range of 10 ∼ 100 kHz. The measured period rms and peak-to-peak jitters are 2.71 ps, rms and 20.6 ps, pp, respectively. The proposed spread-spectrum clock generator is fabricated in a 180 nm CMOS process and occupies an area of 0.525 mm2.