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Five-level hybrid DC-DC converter with enhanced light-load efficiency 提高轻载效率的五电平混合DC-DC变换器
2016 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2016-05-22 DOI: 10.1109/ISCAS.2016.7527209
Abdullah Abdulslam, Farid El-Sehrawy, Y. Ismail
{"title":"Five-level hybrid DC-DC converter with enhanced light-load efficiency","authors":"Abdullah Abdulslam, Farid El-Sehrawy, Y. Ismail","doi":"10.1109/ISCAS.2016.7527209","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7527209","url":null,"abstract":"In this paper, a 5-level hybrid converter is proposed. The circuit structure and the working principle are illustrated. The circuit is capable of providing five different voltage levels at the inductor input with the help of two flying capacitors. By reducing the voltage difference at the inductor input, the 5-level buck converter can use smaller inductors as compared to both 3-level and conventional buck converters which makes it more suitable for on-chip DC-DC conversion. Simulation results on TSMC 65nm technology using 0.5nH on-chip spiral inductor show that the 5-level hybrid converter achieves more than 15% improvement in efficiency over a 3-level buck converter at certain output voltage ranges. A test PCB is also implemented for verification of the functionality and experimental measurements show that the 5-level hybrid converter can achieve better efficiency as compared to conventional and 3-level Buck converters especially at low load currents.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"97 1","pages":"217-220"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78794180","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Design of a reliable RRAM-based PUF for compact hardware security primitives 为紧凑的硬件安全原语设计可靠的基于ram的PUF
2016 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2016-05-22 DOI: 10.1109/ISCAS.2016.7539050
Ayushi Shrivastava, Pai-Yu Chen, Yunhui Cao, Shimeng Yu, C. Chakrabarti
{"title":"Design of a reliable RRAM-based PUF for compact hardware security primitives","authors":"Ayushi Shrivastava, Pai-Yu Chen, Yunhui Cao, Shimeng Yu, C. Chakrabarti","doi":"10.1109/ISCAS.2016.7539050","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7539050","url":null,"abstract":"Physical Unclonable Functions (PUF) have to be highly reliable especially when it is being used along with cryptographic hash modules for key generation. To achieve ultrahigh reliability, the conventional approach employs error correction codes (ECC) based on helper data input. Such an approach not only increases the hardware overhead of the PUF but also reduces the entropy of the system, resulting in both hardware and software security issues. In this paper we design a compact and highly reliable PUF architecture based on resistive random access memory (RRAM). We propose a new design where the sum of the read-out currents of multiple RRAM cells is used for generating one response bit. This method statistically minimizes any early-lifetime failure due to RRAM retention degradation at high temperature or under voltage stress. We employ a device model that is calibrated with IMEC HfOx RRAM experimental data and show that with 8 cells per bit, we can ensure <10-6 Intra-Hamming distance (or >99.9999% reliability) for a lifetime >10 years at 125°C. We embed the RRAM PUF into SHA-256 and show that the hardware overhead of the proposed RRAM PUF based architecture is significantly lower than one that uses a traditional RRAM PUF with ECC.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"1 1","pages":"2326-2329"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76328790","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Hybrid large-area systems: Challenges in interfacing 混合大面积系统:接口方面的挑战
2016 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2016-05-22 DOI: 10.1109/ISCAS.2016.7527505
T. Moy, S. Wagner, W. Rieutort-Louis, Yingzhe Hu, Liechao Huang, J. Sanz-Robinson, J. Sturm, N. Verma
{"title":"Hybrid large-area systems: Challenges in interfacing","authors":"T. Moy, S. Wagner, W. Rieutort-Louis, Yingzhe Hu, Liechao Huang, J. Sanz-Robinson, J. Sturm, N. Verma","doi":"10.1109/ISCAS.2016.7527505","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7527505","url":null,"abstract":"Hybrid large-area systems aim to leverage the strengths of two complementary technologies: (1) large-area electronics (LAE), which enables dense arrays of diverse transducers on substrates that can be large and flexible; and (2) silicon CMOS ICs, which enable efficient and high-performance instrumentation, computation, and power management. A key challenge in realizing these hybrid systems on a large-scale lies in the interfacing required between the two technologies. We describe methods to ease the interfacing, enabled by device, circuit, and algorithmic advances, thereby suggesting a range of challenges and opportunities that are exposed when thinking about systems.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"18 1","pages":"1374-1377"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87511999","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Fast H.264/AVC to HEVC transcoder based on data mining and decision trees 基于数据挖掘和决策树的快速H.264/AVC转HEVC转码器
2016 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2016-05-22 DOI: 10.1109/ISCAS.2016.7539110
G. Corrêa, L. Agostini, L. Cruz
{"title":"Fast H.264/AVC to HEVC transcoder based on data mining and decision trees","authors":"G. Corrêa, L. Agostini, L. Cruz","doi":"10.1109/ISCAS.2016.7539110","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7539110","url":null,"abstract":"High Efficiency Video Coding (HEVC) is gradually replacing its predecessor, the H.264/AVC standard, as the state-of-the-art technology for video compression. However, H.264/AVC has dominated the market for over a decade, so that there is an enormous amount of legacy content that must be migrated. This paper proposes a fast transcoder based on an extensive data mining process on H.264/AVC decoding attributes. The data mining allowed identifying relevant information from the H.264/AVC decoding process, which was conveyed to the C4.5 machine learning algorithm to build a set of decision trees that simplify the complex Coding Unit (CU) size decision in HEVC. Experimental results have shown an average reduction of 44% in the transcoding time, with a small bit rate increase of 1.67%. These results outperform any previous works available in the literature.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"2017 1","pages":"2539-2542"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87788839","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Implementation and design investigation of 40 Gbps driver IC for silicon photonics ring-modulator in SiGe 130-nm sige130 -nm硅光子学环调制器40gbps驱动IC的实现与设计研究
2016 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2016-05-22 DOI: 10.1109/ISCAS.2016.7539072
A. Fatemi, H. Klar, F. Gerfers
{"title":"Implementation and design investigation of 40 Gbps driver IC for silicon photonics ring-modulator in SiGe 130-nm","authors":"A. Fatemi, H. Klar, F. Gerfers","doi":"10.1109/ISCAS.2016.7539072","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7539072","url":null,"abstract":"This paper presents a 40 Gbps micro-ring modulator driver which is designed in 130-nm SiGe technology. The proposed driver IC is optimized for a 2 Vppd output signal swing required for the optical modulator or 1 Vppd if terminated by 50 ohm. The power consumption is only 90 mW operated from a 2.5 V supply voltage. The inductor-less driver architecture consists of a fix-biased cascode topology with capacitive degeneration to improve the bandwidth and output voltage swing while minimizing the number of buffer stage to save power. The silicon area efficient driver occupies only 0.04 mm2. Simulation results exhibit a differential gain of 16 dB over 35 GHz. To the best knowledge of the authors, this driver represents the fastest micro-ring modulator driver IC with low transmitter FOM of only 1.12 pJ/(bit*V).","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"140 1","pages":"2387-2390"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87574134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Energy harvesting ASIC for autonomous sensors 用于自主传感器的能量收集ASIC
2016 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2016-05-22 DOI: 10.1109/ISCAS.2016.7539056
Jarno Salomaa, M. Pulkkinen, T. Haapala, S. Chouhan, K. Halonen
{"title":"Energy harvesting ASIC for autonomous sensors","authors":"Jarno Salomaa, M. Pulkkinen, T. Haapala, S. Chouhan, K. Halonen","doi":"10.1109/ISCAS.2016.7539056","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7539056","url":null,"abstract":"In this paper, we present a blackout and brownout insensitive energy harvesting ASIC for ultra-low power autonomous sensor applications. It utilizes both RF or DC power inputs to deliver a regulated voltage for on-chip and off-chip devices. A voltage limiter has been integrated for overvoltage protection. As the ASIC utilizes two regulators alternately, a kick-start method has been used for switching the operation mode. The ASIC is implemented in a 0.18 μm CMOS process. It is able to use a wide range of input DC voltages (0.8...2 V at -40...85 °C) or input AC powers down to -14 dBm.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"12 1","pages":"2350-2353"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82839927","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A 1-V PTAT current reference circuit with 0.05%/V current sensitivity to VDD 1-V PTAT电流基准电路，对VDD的电流灵敏度为0.05%/V
2016 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2016-05-22 DOI: 10.1109/ISCAS.2016.7527287
Jorge V. de la Cruz, A. Aita
{"title":"A 1-V PTAT current reference circuit with 0.05%/V current sensitivity to VDD","authors":"Jorge V. de la Cruz, A. Aita","doi":"10.1109/ISCAS.2016.7527287","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7527287","url":null,"abstract":"This paper presents a CMOS PTAT current reference circuit which is robust against process and supply voltage variations over a wide voltage and temperature range, i.e. from 0.9 V to 2.5 V and from -40° C to 125° C, respectively. Two implementations of the same circuit were designed for comparison: the first one uses core transistors (1.1 V), while the second one employs IO transistors (2.5 V). The circuit uses a PMOS version of a conventional PTAT current generator with a PMOS self-cascode MOSFET and a PMOS feedback amplifier to enhance the circuit performance. Simulation results have shown a PTAT current sensitivity to the supply voltage of 2.9%/V @ 27° C (from 0.9 V to 1.5 V) and of 0.05%/V @ 27° C (from 1 V to 2.5 V) for core and IO transistors implementations, respectively, and a nearly constant current spread over temperature, with a maximum variation of 10% (3σ) for both ones.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"19 1","pages":"502-505"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90244000","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
HV-CMOS single-chip electronics platform for lab-on-chip DNA analysis 用于芯片上DNA分析的HV-CMOS单芯片电子平台
2016 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2016-05-22 DOI: 10.1109/ISCAS.2016.7539082
David L. Sloan, Benjamin Martin, Gordon Hall, Andrew Hakman, P. Marshall, S. Martel, C. Backhouse, V. Gaudet, D. Elliott
{"title":"HV-CMOS single-chip electronics platform for lab-on-chip DNA analysis","authors":"David L. Sloan, Benjamin Martin, Gordon Hall, Andrew Hakman, P. Marshall, S. Martel, C. Backhouse, V. Gaudet, D. Elliott","doi":"10.1109/ISCAS.2016.7539082","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7539082","url":null,"abstract":"We present a custom integrated circuit (IC) for use in miniaturized genetic test devices with optical coupling with either an optical relay lens or direct surface contact micro-fluidic channels. This IC is capable of high-voltage generation in the 70-300 V range at 10 μA. High-voltage switching circuits for mm-scale capillaries channels with up to 4 electrodes are present. Optical detection with an optical power resolution of 0.46 pW across the diode surface is available for sample detection through a 13-bit analog-to-digital converter. All systems and supporting devices communicate and are powered by a USB connection and fall within the USB 2.0 power budget of 2.5 W.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"7 1","pages":"2427-2430"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79073436","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Charge recovery logic for thermal harvesting applications 热收集应用的电荷恢复逻辑
2016 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2016-05-22 DOI: 10.1109/ISCAS.2016.7527297
Leo Filippini, B. Taskin
{"title":"Charge recovery logic for thermal harvesting applications","authors":"Leo Filippini, B. Taskin","doi":"10.1109/ISCAS.2016.7527297","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7527297","url":null,"abstract":"This paper investigates the substitution of CMOS or near-threshold CMOS with Charge Recovery Logic (CRL) in applications where energy is thermally harvested. By doing so, it is possible to eliminate the bulky DC/DC stage needed to provide the supply voltage for CMOS operation. Instead, a simple LC-tank oscillator is used to generate a power-clock suitable for CRL operation. Simulation results of a 256-stage inverter chain designed in Efficient Charge Recovery Logic (ECRL) are presented. Two additional novelties are presented i) using ECRL at a near-threshold voltage and ii) generating the four-phase power-clock by means of a quadrature oscillator. The traditional, full-swing CMOS system dissipates 18.2× the power dissipated by the proposed TP-ECRL system.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"87 1","pages":"542-545"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83440054","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Some results on stochastic input-to-state stability of stochastic switched nonlinear systems 关于随机切换非线性系统随机输入-状态稳定性的一些结果
2016 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2016-05-22 DOI: 10.1109/ISCAS.2016.7527329
Guangdeng Zong, Zidong Ai, W. Zheng, Jinhu Lu
{"title":"Some results on stochastic input-to-state stability of stochastic switched nonlinear systems","authors":"Guangdeng Zong, Zidong Ai, W. Zheng, Jinhu Lu","doi":"10.1109/ISCAS.2016.7527329","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7527329","url":null,"abstract":"In this paper, the problem of stochastic input-to-state stability (SISS) is investigated for a class of stochastic switched nonlinear systems. A sufficient condition is first derived to estimate an upper bound on a stochastic process. Based on that, the SISS problem is addressed for stochastic nonlinear systems be virtue of the indefinite Lyapuno function approach. For the convenience of simulation, the SISS property of stochastic switched nonlinear systems i further analyzed by the average dwell-time technique. An illustrative example together with numerical simulatio s is presented to demonstrate the efficiency of the proposed results.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"126 1","pages":"670-673"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81174653","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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