{"title":"1-V PTAT电流基准电路,对VDD的电流灵敏度为0.05%/V","authors":"Jorge V. de la Cruz, A. Aita","doi":"10.1109/ISCAS.2016.7527287","DOIUrl":null,"url":null,"abstract":"This paper presents a CMOS PTAT current reference circuit which is robust against process and supply voltage variations over a wide voltage and temperature range, i.e. from 0.9 V to 2.5 V and from -40° C to 125° C, respectively. Two implementations of the same circuit were designed for comparison: the first one uses core transistors (1.1 V), while the second one employs IO transistors (2.5 V). The circuit uses a PMOS version of a conventional PTAT current generator with a PMOS self-cascode MOSFET and a PMOS feedback amplifier to enhance the circuit performance. Simulation results have shown a PTAT current sensitivity to the supply voltage of 2.9%/V @ 27° C (from 0.9 V to 1.5 V) and of 0.05%/V @ 27° C (from 1 V to 2.5 V) for core and IO transistors implementations, respectively, and a nearly constant current spread over temperature, with a maximum variation of 10% (3σ) for both ones.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"19 1","pages":"502-505"},"PeriodicalIF":0.0000,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":"{\"title\":\"A 1-V PTAT current reference circuit with 0.05%/V current sensitivity to VDD\",\"authors\":\"Jorge V. de la Cruz, A. Aita\",\"doi\":\"10.1109/ISCAS.2016.7527287\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a CMOS PTAT current reference circuit which is robust against process and supply voltage variations over a wide voltage and temperature range, i.e. from 0.9 V to 2.5 V and from -40° C to 125° C, respectively. Two implementations of the same circuit were designed for comparison: the first one uses core transistors (1.1 V), while the second one employs IO transistors (2.5 V). The circuit uses a PMOS version of a conventional PTAT current generator with a PMOS self-cascode MOSFET and a PMOS feedback amplifier to enhance the circuit performance. Simulation results have shown a PTAT current sensitivity to the supply voltage of 2.9%/V @ 27° C (from 0.9 V to 1.5 V) and of 0.05%/V @ 27° C (from 1 V to 2.5 V) for core and IO transistors implementations, respectively, and a nearly constant current spread over temperature, with a maximum variation of 10% (3σ) for both ones.\",\"PeriodicalId\":6546,\"journal\":{\"name\":\"2016 IEEE International Symposium on Circuits and Systems (ISCAS)\",\"volume\":\"19 1\",\"pages\":\"502-505\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-05-22\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"9\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 IEEE International Symposium on Circuits and Systems (ISCAS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISCAS.2016.7527287\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISCAS.2016.7527287","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 1-V PTAT current reference circuit with 0.05%/V current sensitivity to VDD
This paper presents a CMOS PTAT current reference circuit which is robust against process and supply voltage variations over a wide voltage and temperature range, i.e. from 0.9 V to 2.5 V and from -40° C to 125° C, respectively. Two implementations of the same circuit were designed for comparison: the first one uses core transistors (1.1 V), while the second one employs IO transistors (2.5 V). The circuit uses a PMOS version of a conventional PTAT current generator with a PMOS self-cascode MOSFET and a PMOS feedback amplifier to enhance the circuit performance. Simulation results have shown a PTAT current sensitivity to the supply voltage of 2.9%/V @ 27° C (from 0.9 V to 1.5 V) and of 0.05%/V @ 27° C (from 1 V to 2.5 V) for core and IO transistors implementations, respectively, and a nearly constant current spread over temperature, with a maximum variation of 10% (3σ) for both ones.