{"title":"一种高效的基于参考的自适应天线阻抗匹配CMOS电路","authors":"A. Robichaud, F. Nabki, D. Deslandes","doi":"10.1109/ISCAS.2016.7527512","DOIUrl":null,"url":null,"abstract":"This paper presents a simple integrated reference based adaptive matching network capable of undertaking real time antenna tuning for applications such as wearable wireless sensors. The signal sent to the antenna is compared to a reference signal using a single flip-flop acting as a phase detector. In case of an impedance mismatch, a counter controlling a capacitor bank is activated reducing the sensed mismatch. The system is capable of three modes: calibration, matching and operation. The calibration mode ensures that the reference signal is in phase with the signal sent to the antenna when the impedance of the antenna is 50 Ω. In matching mode, the capacitor bank is adjusted to maintain antenna matching. In operation mode, the circuit is shut off allowing for low power consumption (85 nW while matching every 1 ms). The circuit is able to provide a VSWR < 2 over a wide range of antenna impedance levels. It is designed in CMOS 0.13 μm technology.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"63 1","pages":"1402-1405"},"PeriodicalIF":0.0000,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"An efficient reference-based adaptive antenna impedance matching CMOS circuit\",\"authors\":\"A. Robichaud, F. Nabki, D. Deslandes\",\"doi\":\"10.1109/ISCAS.2016.7527512\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a simple integrated reference based adaptive matching network capable of undertaking real time antenna tuning for applications such as wearable wireless sensors. The signal sent to the antenna is compared to a reference signal using a single flip-flop acting as a phase detector. In case of an impedance mismatch, a counter controlling a capacitor bank is activated reducing the sensed mismatch. The system is capable of three modes: calibration, matching and operation. The calibration mode ensures that the reference signal is in phase with the signal sent to the antenna when the impedance of the antenna is 50 Ω. In matching mode, the capacitor bank is adjusted to maintain antenna matching. In operation mode, the circuit is shut off allowing for low power consumption (85 nW while matching every 1 ms). The circuit is able to provide a VSWR < 2 over a wide range of antenna impedance levels. It is designed in CMOS 0.13 μm technology.\",\"PeriodicalId\":6546,\"journal\":{\"name\":\"2016 IEEE International Symposium on Circuits and Systems (ISCAS)\",\"volume\":\"63 1\",\"pages\":\"1402-1405\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-05-22\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 IEEE International Symposium on Circuits and Systems (ISCAS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISCAS.2016.7527512\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISCAS.2016.7527512","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An efficient reference-based adaptive antenna impedance matching CMOS circuit
This paper presents a simple integrated reference based adaptive matching network capable of undertaking real time antenna tuning for applications such as wearable wireless sensors. The signal sent to the antenna is compared to a reference signal using a single flip-flop acting as a phase detector. In case of an impedance mismatch, a counter controlling a capacitor bank is activated reducing the sensed mismatch. The system is capable of three modes: calibration, matching and operation. The calibration mode ensures that the reference signal is in phase with the signal sent to the antenna when the impedance of the antenna is 50 Ω. In matching mode, the capacitor bank is adjusted to maintain antenna matching. In operation mode, the circuit is shut off allowing for low power consumption (85 nW while matching every 1 ms). The circuit is able to provide a VSWR < 2 over a wide range of antenna impedance levels. It is designed in CMOS 0.13 μm technology.