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2010 Silicon Nanoelectronics Workshop最新文献

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Irregular resistive switching characteristics and its mechanism based on NiO unipolar switching resistive random access memory (RRAM) 基于NiO单极开关电阻随机存取存储器(RRAM)的不规则电阻开关特性及其机理
2010 Silicon Nanoelectronics Workshop Pub Date : 2010-06-13 DOI: 10.1109/SNW.2010.5562580
K. Ryoo, Jeong-Hoon Oh, Hongsik Jeong, Byung-Gook Park
{"title":"Irregular resistive switching characteristics and its mechanism based on NiO unipolar switching resistive random access memory (RRAM)","authors":"K. Ryoo, Jeong-Hoon Oh, Hongsik Jeong, Byung-Gook Park","doi":"10.1109/SNW.2010.5562580","DOIUrl":"https://doi.org/10.1109/SNW.2010.5562580","url":null,"abstract":"Resistive switching characteristics are investigated for NiO resistive switching random access memory (RRAM) by adapting cross-pointed structure. Uniform transition characteristics from high resistive state (HRS) to low resistive state (LRS) are very important to evaluate high reset/set ratio with low switching current. A cell which shows an irregular switching behavior in the initial transition has been discovered and characteristics associated with it have been discussed. In order to prevent these undesirable effects, optimal process conditions have been addressed.","PeriodicalId":6433,"journal":{"name":"2010 Silicon Nanoelectronics Workshop","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88697298","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Long range pinning interaction in ultra-thin insulator-inserted metal/germanium junctions 超薄绝缘体插入金属/锗结中的长距离钉钉相互作用
2010 Silicon Nanoelectronics Workshop Pub Date : 2010-06-13 DOI: 10.1109/SNW.2010.5562590
T. Nishimura, K. Kita, K. Nagashio, A. Toriumi
{"title":"Long range pinning interaction in ultra-thin insulator-inserted metal/germanium junctions","authors":"T. Nishimura, K. Kita, K. Nagashio, A. Toriumi","doi":"10.1109/SNW.2010.5562590","DOIUrl":"https://doi.org/10.1109/SNW.2010.5562590","url":null,"abstract":"In this paper, we discuss the Fermi Level Pinning (FLP) modulation at metal/germanium (Ge) interface by inserting ultra-thin insulator film. The FLP was alleviated gradually and continuously with increasing insulator (GeO2) thickness up to 2 nm. The results cannot be simply explained by the termination of dangling bonds or defects just at Ge interface. It is inferred that relatively long range (∼ 2 nm) interaction between metal and Ge might be involved in the FLP and its alleviation.","PeriodicalId":6433,"journal":{"name":"2010 Silicon Nanoelectronics Workshop","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79731781","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Nanoscale memories for compute applications 用于计算应用的纳米级存储器
2010 Silicon Nanoelectronics Workshop Pub Date : 2010-06-13 DOI: 10.1109/SNW.2010.5562581
K. Parat
{"title":"Nanoscale memories for compute applications","authors":"K. Parat","doi":"10.1109/SNW.2010.5562581","DOIUrl":"https://doi.org/10.1109/SNW.2010.5562581","url":null,"abstract":"As the performance gap between the CPU and the HDD has increased over time, NAND Flash based Solid State Drive (SSD) has emerged as an ideal candidate to fill this space. While continued cell scaling will further solidify the position of the NAND Flash in the compute applications, eventually it will hit a scaling wall creating opportunities for other types of memories. The vision for such a future memory technology involves a cross-point memory array that will be stackable in the back end CMOS flow and will be scalable to the 10nm half-pitch and below. Some of these memories, depending upon their improved performance over NAND Flash, may also have their unique position in the overall memory hierarchy of a compute system.","PeriodicalId":6433,"journal":{"name":"2010 Silicon Nanoelectronics Workshop","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80517636","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design theory and fabrication process of 90nm unipolar-CMOS 90nm单极cmos的设计理论与制造工艺
2010 Silicon Nanoelectronics Workshop Pub Date : 2010-06-13 DOI: 10.1109/SNW.2010.5562542
Jyi-Tsong Lin, Hsuan-Hsu Chen, Kuan-Yu Lu, Chih-Hung Sun, Y. Eng, C. Kuo, Po-Hsieh Lin, T. Lai, Fu-Liang Yang
{"title":"Design theory and fabrication process of 90nm unipolar-CMOS","authors":"Jyi-Tsong Lin, Hsuan-Hsu Chen, Kuan-Yu Lu, Chih-Hung Sun, Y. Eng, C. Kuo, Po-Hsieh Lin, T. Lai, Fu-Liang Yang","doi":"10.1109/SNW.2010.5562542","DOIUrl":"https://doi.org/10.1109/SNW.2010.5562542","url":null,"abstract":"The innovative basic punchthrough theory for the unipolar-CMOS is for the first time presented and the first unipolar-CMOS inverter has been fabricated successfully by using the 90nm technology developed in Taiwan National Nano Device Lab. The severe scaling issues with silicon can be further use and no more serious. The low-performance P-FETs can be get rid of and switch much faster both for high-electron-mobility III–V and CNT based technology. According to the measurement two empirical models, the new concept of the load line drawing and the optimum design of the unipolar-CMOS are also illustrated. Employing them for unipolar-CMOS design, the desired high performance ultimate SOC and SOP system can be easily realized.","PeriodicalId":6433,"journal":{"name":"2010 Silicon Nanoelectronics Workshop","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91446886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Channel scaling in Si and In0.3Ga0.7As bulk MOSFETs: A Monte Carlo study Si和In0.3Ga0.7As块体mosfet的沟道缩放:蒙特卡罗研究
2010 Silicon Nanoelectronics Workshop Pub Date : 2010-06-13 DOI: 10.1109/SNW.2010.5562543
A. Islam, K. Kalna
{"title":"Channel scaling in Si and In0.3Ga0.7As bulk MOSFETs: A Monte Carlo study","authors":"A. Islam, K. Kalna","doi":"10.1109/SNW.2010.5562543","DOIUrl":"https://doi.org/10.1109/SNW.2010.5562543","url":null,"abstract":"The ITRS predicts that the scaling of planar CMOS technology will continue till the 22 nm [1] technology node and a possible extension is extremely tempting [2]. The desire to continue the scaling of planar technology is driven by lower costs when compared to novel, non-planar technology concepts like multi-gate architectures or nanowires [3]. However, experimental evidence suggests that carrier effective mobility and injection velocity will dramatically lower at very small gate lengths thus prohibiting the possibility of reaching the ballistic regime [4].","PeriodicalId":6433,"journal":{"name":"2010 Silicon Nanoelectronics Workshop","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74962979","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Enhancement of TFET performance using dopant profile-steepening implant and source dopant concentration engineering at tunneling junction 隧道结源掺杂浓度工程及掺杂谱陡化注入增强ttfet性能
2010 Silicon Nanoelectronics Workshop Pub Date : 2010-06-13 DOI: 10.1109/SNW.2010.5562594
G. Han, Y. Yee, P. Guo, Yue Yang, L. Fan, Chunlei Zhan, Y. Yeo
{"title":"Enhancement of TFET performance using dopant profile-steepening implant and source dopant concentration engineering at tunneling junction","authors":"G. Han, Y. Yee, P. Guo, Yue Yang, L. Fan, Chunlei Zhan, Y. Yeo","doi":"10.1109/SNW.2010.5562594","DOIUrl":"https://doi.org/10.1109/SNW.2010.5562594","url":null,"abstract":"All-Silicon Tunneling Field Effect Transistors (TFETs) with relatively high Ion values were fabricated by inserting an N+ pocket between source and channel to achieve sharpening or steepening of the source dopant profile. The source-side pocket or Dopant Profile Steepening Implant (DPSI) can be tuned to engineer the junction abruptness, boost the lateral electric field at the tunnel region, and reduce the tunneling width for Ion enhancement. By designing the DPSI dose and energy, we demonstrate that further enhancement in Ion values can be achieved.","PeriodicalId":6433,"journal":{"name":"2010 Silicon Nanoelectronics Workshop","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90399317","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Dielectric confinement and fluctuations of the local density of state in the source and drain of an ultra scaled SOI NMOS transistor 超尺度SOI NMOS晶体管源极和漏极的介电约束和局域态密度波动
2010 Silicon Nanoelectronics Workshop Pub Date : 2010-06-13 DOI: 10.1109/SNW.2010.5562598
M. Pierre, B. Roche, X. Jehl, M. Sanquer, R. Wacquez, M. Vinet, O. Cueto, B. Previtali, V. Deshpande
{"title":"Dielectric confinement and fluctuations of the local density of state in the source and drain of an ultra scaled SOI NMOS transistor","authors":"M. Pierre, B. Roche, X. Jehl, M. Sanquer, R. Wacquez, M. Vinet, O. Cueto, B. Previtali, V. Deshpande","doi":"10.1109/SNW.2010.5562598","DOIUrl":"https://doi.org/10.1109/SNW.2010.5562598","url":null,"abstract":"We fabricated SOI nanowire MOSFETs with a very small channel volume and few dopants between the highly doped source and drain. The ionization energy of these isolated As dopants can be extracted. We found a much higher energy than calculated value for As in bulk Si. This enhancement is due to the so-called dielectric confinement, because of the proximity of the buried oxide. Transport through this single dopant also enables probing the fluctuations of local density of states in the contacts.","PeriodicalId":6433,"journal":{"name":"2010 Silicon Nanoelectronics Workshop","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85052916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Impact of surface orientation on Vth variability of FinFET 表面取向对FinFET Vth变异性的影响
2010 Silicon Nanoelectronics Workshop Pub Date : 2010-06-13 DOI: 10.1109/SNW.2010.5562562
Yu-Sheng Wu, M. Fan, P. Su
{"title":"Impact of surface orientation on Vth variability of FinFET","authors":"Yu-Sheng Wu, M. Fan, P. Su","doi":"10.1109/SNW.2010.5562562","DOIUrl":"https://doi.org/10.1109/SNW.2010.5562562","url":null,"abstract":"We have investigated the impact of surface orientation on the Vth variability of Si- and Ge-FinFET using both the analytical solution of Schrödinger equation and atomistic simulation. Our study indicates that, for ultra-scaled FinFET, the importance of tch variation increases due to the quantum-confinement effect. The Si-(100) and Ge-(111) surface show lower Vth sensitivity to tch variation as compared with other orientations. On the contrary, the quantum-confinement effect reduces the Vth sensitivity to Leff, and Si-(111) and Ge-(100) surface show lower Vth sensitivity as compared with other orientations. Our study may provide insights for device design and circuit optimization using advanced FinFET technologies.","PeriodicalId":6433,"journal":{"name":"2010 Silicon Nanoelectronics Workshop","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81761148","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Monte Carlo analysis of In0.53Ga0.47as Implant-Free Quantum-Well device performance In0.53Ga0.47as无植入量子阱器件性能的蒙特卡罗分析
2010 Silicon Nanoelectronics Workshop Pub Date : 2010-06-13 DOI: 10.1109/SNW.2010.5562589
B. Benbakhti, E. Towie, K. Kalna, G. Hellings, G. Eneman, K. De Meyer, M. Meuris, A. Asenov
{"title":"Monte Carlo analysis of In0.53Ga0.47as Implant-Free Quantum-Well device performance","authors":"B. Benbakhti, E. Towie, K. Kalna, G. Hellings, G. Eneman, K. De Meyer, M. Meuris, A. Asenov","doi":"10.1109/SNW.2010.5562589","DOIUrl":"https://doi.org/10.1109/SNW.2010.5562589","url":null,"abstract":"III–V nMOSFETs are promising candidates for n-channel high-performance transistors in CMOS in the sub-22 nm technology [1]. High electron mobility and low effective mass resulting in a very high injection velocity and low backscattering promise high device performance [2] at a low supply voltage. Various high-к dielectrics have been developed in order to meet the gate stack requirements of III–V MOSFETs [3]. However the introduction of III–V materials into CMOS requires transistor architectures that can take full advantage of the high mobility in the channel, simultaneously neutralising some of the potentially detrimental effects. Among such architectures, the Implant-Free Quantum-Well (IF-QW) transistor [4] offers interesting technological and performance advantages and tradeoffs (Fig. 1.). The IF-QW device features overgrown, heavily doped Source/Drain (S/D) contacts as a replacement of the conventional implanted junctions. The confinement of the carriers in the quantum well in combination with the p-type substrate doping below the channel provides excellent electrostatic integrity.","PeriodicalId":6433,"journal":{"name":"2010 Silicon Nanoelectronics Workshop","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83967580","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Effect of oxide thickness on the low-frequency noise in MOSFET-based charge transfer devices 氧化物厚度对基于mosfet的电荷转移器件低频噪声的影响
2010 Silicon Nanoelectronics Workshop Pub Date : 2010-06-13 DOI: 10.1109/SNW.2010.5562539
Vipul Singh, H. Inokawa, H. Satoh
{"title":"Effect of oxide thickness on the low-frequency noise in MOSFET-based charge transfer devices","authors":"Vipul Singh, H. Inokawa, H. Satoh","doi":"10.1109/SNW.2010.5562539","DOIUrl":"https://doi.org/10.1109/SNW.2010.5562539","url":null,"abstract":"Current noise in MOSFET-based charge transfer device consisting of different gate oxide thicknesses was evaluated. More than an order of magnitude higher noise levels were found to exist in 5nm thick gate oxide devices compared to 10 and 20 nm thick gate oxide devices as opposed to the theoretical expectation. The normalized noise powers under both CT and DC modes were formulated to be directly correlated to the power of interface charge fluctuation. As a result, normalized noise power was found to be in the order of the interface trap density in these devices, rationalizing the larger noise in the 5 nm gate oxide device.","PeriodicalId":6433,"journal":{"name":"2010 Silicon Nanoelectronics Workshop","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86521739","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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