Channel scaling in Si and In0.3Ga0.7As bulk MOSFETs: A Monte Carlo study

Abstract

The ITRS predicts that the scaling of planar CMOS technology will continue till the 22 nm [1] technology node and a possible extension is extremely tempting [2]. The desire to continue the scaling of planar technology is driven by lower costs when compared to novel, non-planar technology concepts like multi-gate architectures or nanowires [3]. However, experimental evidence suggests that carrier effective mobility and injection velocity will dramatically lower at very small gate lengths thus prohibiting the possibility of reaching the ballistic regime [4].