90nm单极cmos的设计理论与制造工艺

Jyi-Tsong Lin, Hsuan-Hsu Chen, Kuan-Yu Lu, Chih-Hung Sun, Y. Eng, C. Kuo, Po-Hsieh Lin, T. Lai, Fu-Liang Yang
{"title":"90nm单极cmos的设计理论与制造工艺","authors":"Jyi-Tsong Lin, Hsuan-Hsu Chen, Kuan-Yu Lu, Chih-Hung Sun, Y. Eng, C. Kuo, Po-Hsieh Lin, T. Lai, Fu-Liang Yang","doi":"10.1109/SNW.2010.5562542","DOIUrl":null,"url":null,"abstract":"The innovative basic punchthrough theory for the unipolar-CMOS is for the first time presented and the first unipolar-CMOS inverter has been fabricated successfully by using the 90nm technology developed in Taiwan National Nano Device Lab. The severe scaling issues with silicon can be further use and no more serious. The low-performance P-FETs can be get rid of and switch much faster both for high-electron-mobility III–V and CNT based technology. According to the measurement two empirical models, the new concept of the load line drawing and the optimum design of the unipolar-CMOS are also illustrated. Employing them for unipolar-CMOS design, the desired high performance ultimate SOC and SOP system can be easily realized.","PeriodicalId":6433,"journal":{"name":"2010 Silicon Nanoelectronics Workshop","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2010-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Design theory and fabrication process of 90nm unipolar-CMOS\",\"authors\":\"Jyi-Tsong Lin, Hsuan-Hsu Chen, Kuan-Yu Lu, Chih-Hung Sun, Y. Eng, C. Kuo, Po-Hsieh Lin, T. Lai, Fu-Liang Yang\",\"doi\":\"10.1109/SNW.2010.5562542\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The innovative basic punchthrough theory for the unipolar-CMOS is for the first time presented and the first unipolar-CMOS inverter has been fabricated successfully by using the 90nm technology developed in Taiwan National Nano Device Lab. The severe scaling issues with silicon can be further use and no more serious. The low-performance P-FETs can be get rid of and switch much faster both for high-electron-mobility III–V and CNT based technology. According to the measurement two empirical models, the new concept of the load line drawing and the optimum design of the unipolar-CMOS are also illustrated. Employing them for unipolar-CMOS design, the desired high performance ultimate SOC and SOP system can be easily realized.\",\"PeriodicalId\":6433,\"journal\":{\"name\":\"2010 Silicon Nanoelectronics Workshop\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-06-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2010 Silicon Nanoelectronics Workshop\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SNW.2010.5562542\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 Silicon Nanoelectronics Workshop","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SNW.2010.5562542","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2

摘要

首次提出了单极cmos的创新基本穿孔理论,并利用台湾国家纳米器件实验室开发的90纳米技术成功制造了第一台单极cmos逆变器。硅的严重结垢问题可以进一步使用,不会更严重。对于高电子迁移率III-V和基于碳纳米管的技术,可以更快地摆脱和切换低性能的p - fet。根据实测的两个经验模型,说明了绘制负载线的新概念和单极cmos的优化设计。将它们用于单极cmos设计,可以轻松实现理想的高性能SOC和SOP系统。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Design theory and fabrication process of 90nm unipolar-CMOS
The innovative basic punchthrough theory for the unipolar-CMOS is for the first time presented and the first unipolar-CMOS inverter has been fabricated successfully by using the 90nm technology developed in Taiwan National Nano Device Lab. The severe scaling issues with silicon can be further use and no more serious. The low-performance P-FETs can be get rid of and switch much faster both for high-electron-mobility III–V and CNT based technology. According to the measurement two empirical models, the new concept of the load line drawing and the optimum design of the unipolar-CMOS are also illustrated. Employing them for unipolar-CMOS design, the desired high performance ultimate SOC and SOP system can be easily realized.
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