2012 IEEE 62nd Electronic Components and Technology Conference最新文献

{"title":"Void formation during reflow soldering","authors":"Thomas D. Ewald, Norbert Holle, Klaus-Jurgen Wolter","doi":"10.1109/ECTC.2012.6249064","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6249064","url":null,"abstract":"In the present study the interaction between solder paste and the PCB surface finish and its impact on void formation was investigated. Therefore, a comprehensive set of tests was performed on test vehicles with different diameter of the solder powder, solder alloy composition, PCB surface finish and flux chemistry. Based on these experimental results a hypothesis of void generating mechanisms is presented characterizing the wetting process.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":"32 1","pages":"1677-1683"},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82925253","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Effect of Joule heating on electromigration reliability of Pb-free interconnect","authors":"Minhua Lu, S. Wright, Gerard McVicker, S. M. Sri-Jayantha","doi":"10.1109/ECTC.2012.6248890","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6248890","url":null,"abstract":"Temperature and current are two major parameters that impact electromigration reliability. Due to the large current used in the accelerated electromigration test, the Joule self-heating associated with the stress current can be significant. The paper presents a study of electromigration fails in Pb-free interconnect from the point of view of localized Joule heating. The Joule heating effect in two types of packages, a fully assembled flip chip module with standard C4s and a silicon to silicon assembly with microbumps, is considered. A thermal FEM model is used as a guide to interpret the experimental observations.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":"80 1","pages":"590-596"},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81070293","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Non-conductive film and compression molding technology for self-assembly-based 3D integration","authors":"T. Fukushima, Y. Ohara, J. Bea, M. Murugesan, K. Lee, T. Tanaka, M. Koyanagi","doi":"10.1109/ECTC.2012.6248860","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6248860","url":null,"abstract":"Two key technologies consisting of chip-to-wafer bonding through a non-conductive film (NCF) and wafer-level packaging using compression molding were studied for self-assembly-based 3D integration, especially reconfigured wafer-to-wafer stacking. 4-mm-by-5-mm chips having 20-μm-pitch Cu-SnAg microbumps were successfully bonded to wafers through NCF. The resulting daisy chain obtained from the chip-to-wafer structure showed low contact resistance of approximately 50 MΩ/bump. Compression molding was implemented to a chip-on-wafer structure. Grinding of the chip-on-wafer structure gave low total thickness variation (TTV) within 1 μm and the following CMP led good planarization capability.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":"101 1","pages":"393-398"},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81053187","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Low slow-wave effect and crosstalk for low-cost ABF-coated TSVs in 3-D IC interposer","authors":"Yu-Jen Chang, Tai-Yu Zheng, Hao-Hsiang Chuang, Chuen-De Wang, P. Chen, T. Kuo, C. Zhan, Shih-Hsien Wu, W. Lo, Yi-Chang Lu, Y. Chiou, Tzong-Lin Wu","doi":"10.1109/ECTC.2012.6249103","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6249103","url":null,"abstract":"A solution for reducing the signal distortion in SiO2-coated through silicon vias (TSVs) is proposed. The mechanism can be explained by using a verified equivalent circuit model of a four-TSV system. Based on this circuit model, the phenomena that larger thickness of dielectric layer causes lower slow-wave factor (SWF), smaller insertion loss and smaller crosstalk level can be observed. With the aid of ajinomoto-build-up-film-coated (ABF-coated) TSVs, the solution can be implemented. The insertion loss is 3 dB better, the near-end crosstalk is 5 dB better, and the far-end crosstalk is 25dB better than conventional SiO2-coated TSVs at 2 GHz. Measurement results are also given. Good consistency can be seen, and can support the conclusion of the simulation results.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":"18 1","pages":"1934-1938"},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88838731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Failsafe wafer-level packaging of a piezoelectric MEMS actuator","authors":"M. Matin, K. Ozaki, D. Akai, K. Sawada, M. Ishida","doi":"10.1109/ECTC.2012.6248855","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6248855","url":null,"abstract":"Micro-electro-mechanical systems (MEMS) technology can offer a viable alternative to realize miniaturized and less expensive actuators for deformable mirror in adaptive optics for high resolution retinal imaging. However, during fabrication of such devices, functional multilayered thin films are generally deposited at elevated temperatures. These films are therefore subjected to residual stresses which may result in bending of the structure. The bending thus occurred may lead to failure at interfaces between films. A successful fabrication of device therefore relies on the engineering justification of multi-structured device design and growth parameters used in fabrication. In this paper, we present the design of a piezoelectric (ceramic) thin film based MEMS actuator for deformable mirror used in retinal imaging. A proto-type piezoelectric thin film actuator has been fabricated epitaxially using Pt/PZT/SRO/Pt/γ-Al2O3/Si structure. Advanced 3D finite element simulations were conducted to correlate the bending of fabricated structure with residual stresses. A smart alternative design was also proposed employing an extra layer of aluminium in the diaphragm region. Simulation results predict a failsafe structure when the thickness of extra Al-layer is tailored to an optimal thickness. The outcome of this research can be used to overcome the challenge encountered (bending due to residual stresses) to obtain a failsafe wafer-level packaged MEMS actuator for deformable mirror.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":"65 1","pages":"356-361"},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87069456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"2.5D and 3D technology challenges and test vehicle demonstrations","authors":"J. Knickerbocker, P. Andry, E. Colgan, B. Dang, T. Dickson, X. Gu, C. Haymes, C. Jahnes, Y. Liu, J. Maria, R. Polastre, C. Tsang, L. Turlapati, B. Webb, L. Wiggins, S. Wright","doi":"10.1109/ECTC.2012.6248968","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6248968","url":null,"abstract":"Three-dimensional (3D) chip integration with through-silicon-vias (TSV's) can enable system benefits of enhanced performance, power efficiency, and cost reduction leveraging micro-architecture designs such as 2.5D silicon packages and 3D die stacks. 2.5D silicon packages and 3D die stacks structures integrated in modules each have unique technical challenges but each can provide system benefits including lower latency and higher bandwidth compared to traditional packaging solutions. Additional system benefits using 2.5D or 3D integration can include product miniaturization or increased function in the same size product. Leveraging proper design and micro-architecture for a system application, 3D technology can aide chip manufacturability for lower costs, sub-component heterogeneous integration, modular design and sub-component design reuse, which can reduce development expense and decrease time to market. 2.5D and 3D technology can reduce interconnection length between circuits leading to lower power consumption and lower latency as well as increase the number of interconnections which supports increased bandwidth to traditional 2D off chip interconnection. Appropriate design ground rules, clocking, and electrical models should match well defined technology attributes such as TSV's and silicon to silicon interconnection electrical parametrics. In addition a wafer test methodology for known good die (KGD) and high yield assembly integration approach are important to obtain integrated 2.5D and 3D modules. For complex 3D integration, proper consideration for module or integrated die stacked with TSV's and Si to Si interconnection may require redundancy and an integral repair methodology. 2.5D and 3D technology challenges may include an increase in the power delivery and cooling requirements to meet the increased circuit density and power density of these structures. For small, low power applications such as mobile devices, 2.5D and 3D technology can provide substantial benefit through both performance benefit and power savings and lead to longer battery life for the same function. For some high performance and high power applications, the 2.5D approach simplifies heterogeneous die integration without requiring leading to increases power density and heat removal cooling density. Whereas some high performance and high power applications using 3D technology may require extensive planning for power delivery with localized power regulation and specialized cooling approaches to avoid excessive in die stack temperatures while taking advantage of performance gains that these short links between heterogeneous die can provide. 3D die stacks using multi-core processors and wide I/O DRAM, eDRAM, SRAM or cache stacks can provide high bandwidth, performance improvements with lower latency. In addition to the power delivery and thermal challenges of 2.5D and 3D described above, there are 3D fabrication and industry compatibility challenges. Technology challenges i","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":"19 1","pages":"1068-1076"},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87513698","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A study on the intermetallic growth of fine-pitch Cu pillar/SnAg solder bump for 3D-TSV interconnection","authors":"Y. Park, Jiwon Shin, Yong-Won Choi, K. Paik","doi":"10.1109/ECTC.2012.6249123","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6249123","url":null,"abstract":"The IMC growth of fine pitch Cu pillar/SnAg solder bumps used for the chip to chip eutectic bonding of 3D-TSV interconnection was investigated. Most of SnAg solder was rapidly consumed by Cu-Sn intermetallic compound (IMC) growth during the eutectic bonding process. The composition of the IMC phase were identified as Cu-Au-Sn ternary phase and the main TEM diffraction patterns were well matched with the Cu6Sn5 crystal structure and the two week diffraction spots between every two strong spots matched with the superlattice of Au atoms. As a result, it was proved that the Cu-Au-Sn ternary IMCs were (Cu, Au)6Sn5. In the case of a large solder joint such as BGA (Ball Grid Array) or CSP (Chip Scale Package), most of the Au deposited on a metal pad was dissolved in the melting solder region due to relatively little Au content. However, in the case of TSV Cu pillar/SnAg solder bump jointed on the Au coated Cu pad, Au atoms were completely dissolved in the solder and participated in the IMC reaction due to the very small amount of solder.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":"58 1","pages":"2053-2056"},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87152173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Remedies to control electromigration: Effects of CNT doped Sn-Ag-Cu interconnects","authors":"Sha Xu, Xiaoxin Zhu, H. Kotadia, Hua Lu, S. Mannan, C. Bailey, Y. Chan","doi":"10.1109/ECTC.2012.6249097","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6249097","url":null,"abstract":"Electromigration is a critical reliability problem in electronic industry, especially with the shrinkage and downscaling of microelectronic feature size, which results in gradual increase of current density. Carbon nanotube(CNT) doping is adopted in this paper. CNT has demonstrated high electromigration resistance. In our work, CNT doping is combined with SAC interconnects. A CNT after surfactant will be incorporated into SAC solder interconnection. Best percentage of CNT doping is found from this experiment, and better electromigration reliability can be observed from this work by SEM image. Moreover, the shear stress distribution is improved using computational study, which shows better mechanical properties. The combination of experimental and numerical study is highlighted in this work.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":"40 6 1","pages":"1899-1904"},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89986469","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Electrical characterization method to study barrier integrity in 3D through-silicon vias","authors":"Y. Li, D. Velenis, T. Kauerauf, M. Stucchi, Y. Civale, A. Redolfi, K. Croes","doi":"10.1109/ECTC.2012.6248846","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6248846","url":null,"abstract":"In this paper, the controlled I-V (IVctrl) method is adopted for the barrier integrity characterization of TSVs at wafer level. Planar capacitor structures are used for the initial validation of the IVctrl method with respect to the traditional time dependent dielectric breakdown (TDDB) methodology. The TDDB field acceleration factor of the TSV liner is extracted by IVctrl in a reasonable time, and the results demonstrate that defective barriers can degrade TDDB field acceleration factor and thus TSV liner reliability.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":"9 1","pages":"304-308"},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89986741","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"3D-TSV vertical interconnection method using Cu/SnAg double bumps and B-stage non-conductive adhesives (NCAs)","authors":"Yong-Won Choi, Jiwon Shin, K. Paik","doi":"10.1109/ECTC.2012.6248969","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6248969","url":null,"abstract":"In this study, the chip to chip eutectic solder bonding method using NCAs for TSV stacking was investigated as an alternative 3D-TSV interconnection method. The non-conductive polymer adhesive was applied at TSV wafers as a film format before eutectic solder bonding resulting in no extra underfill process. The electrical interconnections between micro-sized bumps for TSVs of the stacked chips were investigated. The electrical interconnection through the arrays of the bumps between two chips showed no change even after the reliability tests which meant that vertical interconnection by one step metal/polymer hybrid bonding was rapid as well as stable.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":"1 1","pages":"1077-1080"},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85227357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}