T. Fukushima, Y. Ohara, J. Bea, M. Murugesan, K. Lee, T. Tanaka, M. Koyanagi
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引用次数: 12
摘要
研究了基于自组装的三维集成的两个关键技术,即通过非导电薄膜(NCF)的晶片键合和使用压缩成型的晶片级封装,特别是重新配置的晶片到晶片堆叠。具有20 μm间距Cu-SnAg微凸起的4 mm × 5 mm芯片通过NCF成功结合到晶圆上。从芯片到晶圆结构得到的菊花链显示出约50 MΩ/bump的低接触电阻。对片上芯片结构进行了压缩成型。对片上晶片结构进行磨削后,总厚度变化(TTV)在1 μm以内,磨削后的CMP具有良好的平面化能力。
Non-conductive film and compression molding technology for self-assembly-based 3D integration
Two key technologies consisting of chip-to-wafer bonding through a non-conductive film (NCF) and wafer-level packaging using compression molding were studied for self-assembly-based 3D integration, especially reconfigured wafer-to-wafer stacking. 4-mm-by-5-mm chips having 20-μm-pitch Cu-SnAg microbumps were successfully bonded to wafers through NCF. The resulting daisy chain obtained from the chip-to-wafer structure showed low contact resistance of approximately 50 MΩ/bump. Compression molding was implemented to a chip-on-wafer structure. Grinding of the chip-on-wafer structure gave low total thickness variation (TTV) within 1 μm and the following CMP led good planarization capability.