电路与系统(英文)最新文献_第5页

MISO-Type Voltage-Mode Universal Biquadratic Filter Using Single Universal Voltage Conveyor 采用单一通用电压传送器的MISO型电压模式通用双二次滤波器

电路与系统(英文) Pub Date : 2017-09-25 DOI: 10.4236/CS.2017.89015

K. L. Pushkar, Kavya Gupta

引用次数: 6

A Fast FPGA Implementation for Triple DES Encryption Scheme 三重DES加密方案的快速FPGA实现

电路与系统(英文) Pub Date : 2017-09-25 DOI: 10.4236/CS.2017.89016

E. D. Rosal, Sanjeev Kumar

{"title":"A Fast FPGA Implementation for Triple DES Encryption Scheme","authors":"E. D. Rosal, Sanjeev Kumar","doi":"10.4236/CS.2017.89016","DOIUrl":"https://doi.org/10.4236/CS.2017.89016","url":null,"abstract":"In cryptography, the Triple DES (3DES, TDES or officially TDEA) is a symmetric-key block cipher which applies the Data Encryption Standard (DES) cipher algorithm three times to each data block. Electronic payment systems are known to use the TDES scheme for the encryption/decryption of data, and hence faster implementations are of great significance. Field Programmable Gate Arrays (FPGAs) offer a new solution for optimizing the performance of applications meanwhile the Triple Data Encryption Standard (TDES) offers a mean to secure information. In this paper we present a pipelined implementation in VHDL, in Electronic Code Book (EBC) mode, of this commonly used cryptography scheme with aim to improve performance. We achieve a 48-stage pipeline depth by implementing a TDES key buffer and right rotations in the DES decryption key scheduler. Using the Altera Cyclone II FPGA as our platform, we design and verify the implementation with the EDA tools provided by Altera. We gather cost and throughput information from the synthesis and timing results and compare the performance of our design to common implementations presented in other literatures. Our design achieves a throughput of 3.2 Gbps with a 50 MHz clock; a performance increase of up to 16 times.","PeriodicalId":63422,"journal":{"name":"电路与系统(英文)","volume":"08 1","pages":"237-246"},"PeriodicalIF":0.0,"publicationDate":"2017-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49550603","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 13

A Connectivity-Based Legalization Scheme for Standard Cell Placement 一种基于连通性的标准单元布局合法化方案

电路与系统(英文) Pub Date : 2017-08-28 DOI: 10.4236/CS.2017.88013

Antonios N. Dadaliaris, P. Oikonomou, M. Koziri, Evangelia Nerantzaki, Thanasis Loukopoulos, G. Stamoulis

引用次数: 4

Fuzzy Logic Controller Implementation of Power Quality Improvement Using UPQC 用UPQC实现电能质量改善的模糊控制器

电路与系统(英文) Pub Date : 2017-08-28 DOI: 10.4236/CS.2017.88014

S. Balaslubramaniyan, T. S. Sivakumaran

引用次数: 1

THD Analysis of Cascaded H-Bridge Inverter with Fuzzy Logic Controller 模糊控制器级联h桥逆变器的THD分析

电路与系统(英文) Pub Date : 2017-07-18 DOI: 10.4236/CS.2017.87011

N. Sivakumar, A. Sumathi

{"title":"THD Analysis of Cascaded H-Bridge Inverter with Fuzzy Logic Controller","authors":"N. Sivakumar, A. Sumathi","doi":"10.4236/CS.2017.87011","DOIUrl":"https://doi.org/10.4236/CS.2017.87011","url":null,"abstract":"In recent days, the multilevel inverter technology is widely applied to domestic \u0000and industrial applications for medium voltage conversion. But, the power \u0000quality issues of the multilevel inverter limit the usage of much sensitive \u0000equipment like medical instruments. The lower distortion level of the output \u0000voltage and current can generate a quality sinusoidal output voltage in inverters \u0000and they can be used for many applications. The harmonics can cause \u0000major problems in equipments due to the nonlinear loads connected with the \u0000power system. So, it is necessary to minimize the losses to raise its overall efficiency. \u0000In this paper, a new topology of seven level asymmetrical cascaded \u0000H-bridge multilevel inverter with a Fuzzy logic controller had been implemented \u0000to reduce the Total Harmonic Distortion (THD) and to improve the \u0000overall performance of the inverter. The proposed model is well suited for use \u0000with a solar PV application. In this topology, only six IGBT switches are used \u0000with three different voltage ratings of PV modules (1:2:4). The lower number \u0000of semiconductor switches leads to minimizing overall di/dt ratings and voltage \u0000stress on each switches and switching losses. The gate pulses generated by \u0000Sinusoidal Pulse Width Modulation (SPWM) technique with a Fuzzy logic \u0000controller are also introduced. A buck-boost converter is used to maintain the \u0000constant PV voltage level integrated by an MPPT technique followed by Perturb \u0000and Observer algorithm is also implemented. The MPPT is used to harness \u0000the maximum power of solar radiations under its various climatic conditions. \u0000The new topology is evaluated by a Matlab/Simulink model and compared \u0000with a hardware model. The results proved that the THD achieved by \u0000this topology is 1.66% and realized that it meets the IEEE harmonic standards.","PeriodicalId":63422,"journal":{"name":"电路与系统(英文)","volume":"08 1","pages":"171-183"},"PeriodicalIF":0.0,"publicationDate":"2017-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"42349694","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Heart Diseases Diagnosis Using Intelligent Algorithm Based on PCG Signal Analysis 基于PCG信号分析的智能算法在心脏病诊断中的应用

电路与系统(英文) Pub Date : 2017-07-18 DOI: 10.4236/CS.2017.87012

Mohammed Nabih-Ali, E. El-Dahshan, Ashraf S Yahia

引用次数: 28

A Multithreaded CGRA for Convolutional Neural Network Processing 一个用于卷积神经网络处理的多线程CGRA

电路与系统(英文) Pub Date : 2017-06-29 DOI: 10.4236/CS.2017.86010

Kota Ando, Shinya Takamaeda-Yamazaki, M. Ikebe, T. Asai, M. Motomura

{"title":"A Multithreaded CGRA for Convolutional Neural Network Processing","authors":"Kota Ando, Shinya Takamaeda-Yamazaki, M. Ikebe, T. Asai, M. Motomura","doi":"10.4236/CS.2017.86010","DOIUrl":"https://doi.org/10.4236/CS.2017.86010","url":null,"abstract":"Convolutional neural network (CNN) is an essential model to achieve high accuracy in various machine learning applications, such as image recognition and natural language processing. One of the important issues for CNN acceleration with high energy efficiency and processing performance is efficient data reuse by exploiting the inherent data locality. In this paper, we propose a novel CGRA (Coarse Grained Reconfigurable Array) architecture with time-domain multithreading for exploiting input data locality. The multithreading on each processing element enables the input data reusing through multiple computation periods. This paper presents the accelerator design performance analysis of the proposed architecture. We examine the structure of memory subsystems, as well as the architecture of the computing array, to supply required data with minimal performance overhead. We explore efficient architecture design alternatives based on the characteristics of modern CNN configurations. The evaluation results show that the available bandwidth of the external memory can be utilized efficiently when the output plane is wider (in earlier layers of many CNNs) while the input data locality can be utilized maximally when the number of output channel is larger (in later layers).","PeriodicalId":63422,"journal":{"name":"电路与系统(英文)","volume":"08 1","pages":"149-170"},"PeriodicalIF":0.0,"publicationDate":"2017-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"70482126","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

28-nm UTBB FD-SOI vs. 22-nm Tri-Gate FinFET Review: A Designer Guide—Part II 28纳米UTBB FD-SOI与22纳米三栅极FinFET回顾:设计师指南-第二部分

电路与系统(英文) Pub Date : 2017-05-19 DOI: 10.4236/CS.2017.85007

Ali Mohsen, A. Harb, N. Deltimple, Abraham Serhane

引用次数: 4

A High Performance and Energy Efficient Microprocessor with a Novel Restricted Dynamically Reconfigurable Accelerator 一种具有新型受限动态可重构加速器的高性能节能微处理器

电路与系统(英文) Pub Date : 2017-05-19 DOI: 10.4236/CS.2017.85009

Itaru Hida, Shinya Takamaeda-Yamazaki, M. Ikebe, M. Motomura, T. Asai

{"title":"A High Performance and Energy Efficient Microprocessor with a Novel Restricted Dynamically Reconfigurable Accelerator","authors":"Itaru Hida, Shinya Takamaeda-Yamazaki, M. Ikebe, M. Motomura, T. Asai","doi":"10.4236/CS.2017.85009","DOIUrl":"https://doi.org/10.4236/CS.2017.85009","url":null,"abstract":"In the era of Internet of Things, the battery life of edge devices must be extended for sensing connection to the Internet. We aim to reduce the power consumption of the microprocessor embedded in such devices by using a novel dynamically reconfigurable accelerator. Conventional microprocessors consume a large amount of power for memory access, in registers, and for the control of the processor itself rather than computation; this decreases the energy efficiency. Dynamically reconfigurable accelerators reduce such redundant power by computing in parallel on reconfigurable switches and processing element arrays (often consisting of an arithmetic logic unit (ALU) and registers). We propose a novel dynamically reconfigurable accelerator “DYNaSTA” composed of a dynamically reconfigurable data path and static ALU arrays. The static ALU arrays process instructions in parallel without registers and improve energy efficiency. The dynamically reconfigurable data path includes registers and many switches dynamically reconfigured to resolve operand dependencies between instructions mapped on the static ALU array, and forwards appropriate operands to the static ALU array. Therefore, the DYNaSTA accelerator has more flexibility while improving the energy efficiency compared with the conventional dynamically reconfigurable accelerators. We simulated the power consumption of the proposed DYNaSTA accelerator and measured the fabricated chip. As a result, the power consumption was reduced by 69% to 86%, and the energy efficiency improved 4.5 to 13 times compared to a general RISC microprocessor.","PeriodicalId":63422,"journal":{"name":"电路与系统(英文)","volume":"08 1","pages":"134-147"},"PeriodicalIF":0.0,"publicationDate":"2017-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"45208284","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Pencil Beam Grid Antenna Array for Hyperthermia Breast Cancer Treatment System 用于癌症乳腺热疗系统的笔形束栅天线阵列

电路与系统(英文) Pub Date : 2017-05-19 DOI: 10.4236/CS.2017.85008

M. Tayel, T. Abouelnaga, A. Elnagar

{"title":"Pencil Beam Grid Antenna Array for Hyperthermia Breast Cancer Treatment System","authors":"M. Tayel, T. Abouelnaga, A. Elnagar","doi":"10.4236/CS.2017.85008","DOIUrl":"https://doi.org/10.4236/CS.2017.85008","url":null,"abstract":"In this paper, efficient, high gain and pencil beam grid antenna array is proposed for hyperthermia breast cancer therapy system. The proposed \u0000antenna bandwidth extends from 4.8 GHz to 4.9 GHz at resonant frequency of 4.86 GHz. This frequency band has been reported for \u0000the breast cancer hyperthermia therapy. The grid long and short sides are responsible for \u0000the undesired cross-polarized radiation and desired copolarized radiation, \u0000respectively. The unsuitability of the conventional grid antenna array is \u0000ensured by investigating its radiation properties. The proposed grid antenna \u0000array short side width is varied and its long side width is kept wide as \u0000possible to enhance the radiation properties and to reduce the losses. Also, a \u0000reflector has been used for gain enhancement purpose. The proposed grid antenna array achieves side lobe level and 3 dB beam width of —27.9 dB and 25.9° for the E-plane and —27.9 dB and 26.3° for the H-plane, respectively. The breast phantom is irradiated by both proposed and conventional grid \u0000antenna arrays for 10 minutes. The proposed grid antenna array achieves 8°C temperature increase within the breast phantom area compared to 2°C \u0000temperature increase for conventional one. The proposed grid antenna array is highly efficient, high gain and light weight, and it has a very suitable \u0000radiation property for hyperthermia breast \u0000cancer therapy.","PeriodicalId":63422,"journal":{"name":"电路与系统(英文)","volume":"08 1","pages":"122-133"},"PeriodicalIF":0.0,"publicationDate":"2017-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"48676246","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5