{"title":"三重DES加密方案的快速FPGA实现","authors":"E. D. Rosal, Sanjeev Kumar","doi":"10.4236/CS.2017.89016","DOIUrl":null,"url":null,"abstract":"In cryptography, the Triple DES (3DES, TDES or officially TDEA) is a symmetric-key block cipher which applies the Data Encryption Standard (DES) cipher algorithm three times to each data block. Electronic payment systems are known to use the TDES scheme for the encryption/decryption of data, and hence faster implementations are of great significance. Field Programmable Gate Arrays (FPGAs) offer a new solution for optimizing the performance of applications meanwhile the Triple Data Encryption Standard (TDES) offers a mean to secure information. In this paper we present a pipelined implementation in VHDL, in Electronic Code Book (EBC) mode, of this commonly used cryptography scheme with aim to improve performance. We achieve a 48-stage pipeline depth by implementing a TDES key buffer and right rotations in the DES decryption key scheduler. Using the Altera Cyclone II FPGA as our platform, we design and verify the implementation with the EDA tools provided by Altera. We gather cost and throughput information from the synthesis and timing results and compare the performance of our design to common implementations presented in other literatures. Our design achieves a throughput of 3.2 Gbps with a 50 MHz clock; a performance increase of up to 16 times.","PeriodicalId":63422,"journal":{"name":"电路与系统(英文)","volume":"08 1","pages":"237-246"},"PeriodicalIF":0.0000,"publicationDate":"2017-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"13","resultStr":"{\"title\":\"A Fast FPGA Implementation for Triple DES Encryption Scheme\",\"authors\":\"E. D. Rosal, Sanjeev Kumar\",\"doi\":\"10.4236/CS.2017.89016\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In cryptography, the Triple DES (3DES, TDES or officially TDEA) is a symmetric-key block cipher which applies the Data Encryption Standard (DES) cipher algorithm three times to each data block. Electronic payment systems are known to use the TDES scheme for the encryption/decryption of data, and hence faster implementations are of great significance. Field Programmable Gate Arrays (FPGAs) offer a new solution for optimizing the performance of applications meanwhile the Triple Data Encryption Standard (TDES) offers a mean to secure information. In this paper we present a pipelined implementation in VHDL, in Electronic Code Book (EBC) mode, of this commonly used cryptography scheme with aim to improve performance. We achieve a 48-stage pipeline depth by implementing a TDES key buffer and right rotations in the DES decryption key scheduler. Using the Altera Cyclone II FPGA as our platform, we design and verify the implementation with the EDA tools provided by Altera. We gather cost and throughput information from the synthesis and timing results and compare the performance of our design to common implementations presented in other literatures. Our design achieves a throughput of 3.2 Gbps with a 50 MHz clock; a performance increase of up to 16 times.\",\"PeriodicalId\":63422,\"journal\":{\"name\":\"电路与系统(英文)\",\"volume\":\"08 1\",\"pages\":\"237-246\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-09-25\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"13\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"电路与系统(英文)\",\"FirstCategoryId\":\"1093\",\"ListUrlMain\":\"https://doi.org/10.4236/CS.2017.89016\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"电路与系统(英文)","FirstCategoryId":"1093","ListUrlMain":"https://doi.org/10.4236/CS.2017.89016","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 13
摘要
在密码学中,三重DES(3DES、TDES或正式的TDEA)是一种对称密钥块密码,它将数据加密标准(DES)密码算法应用于每个数据块三次。众所周知,电子支付系统使用TDES方案来加密/解密数据,因此更快的实现具有重要意义。现场可编程门阵列(FPGA)为优化应用程序的性能提供了一种新的解决方案,同时三重数据加密标准(TDES)为信息安全提供了手段。在本文中,我们提出了一种在VHDL中以电子代码簿(EBC)模式实现的这种常用密码方案的流水线实现,旨在提高性能。我们通过在DES解密密钥调度器中实现TDES密钥缓冲器和右旋转来实现48级流水线深度。以Altera Cyclone II FPGA为平台,利用Altera提供的EDA工具对其实现进行了设计和验证。我们从合成和时序结果中收集成本和吞吐量信息,并将我们的设计性能与其他文献中介绍的常见实现进行比较。我们的设计在50 MHz时钟下实现了3.2 Gbps的吞吐量;性能提高了16倍。
A Fast FPGA Implementation for Triple DES Encryption Scheme
In cryptography, the Triple DES (3DES, TDES or officially TDEA) is a symmetric-key block cipher which applies the Data Encryption Standard (DES) cipher algorithm three times to each data block. Electronic payment systems are known to use the TDES scheme for the encryption/decryption of data, and hence faster implementations are of great significance. Field Programmable Gate Arrays (FPGAs) offer a new solution for optimizing the performance of applications meanwhile the Triple Data Encryption Standard (TDES) offers a mean to secure information. In this paper we present a pipelined implementation in VHDL, in Electronic Code Book (EBC) mode, of this commonly used cryptography scheme with aim to improve performance. We achieve a 48-stage pipeline depth by implementing a TDES key buffer and right rotations in the DES decryption key scheduler. Using the Altera Cyclone II FPGA as our platform, we design and verify the implementation with the EDA tools provided by Altera. We gather cost and throughput information from the synthesis and timing results and compare the performance of our design to common implementations presented in other literatures. Our design achieves a throughput of 3.2 Gbps with a 50 MHz clock; a performance increase of up to 16 times.