电路与系统(英文)Pub Date : 2017-03-31DOI: 10.4236/CS.2017.83005
J. Athena, V. Sumathy
{"title":"Survey on Public Key Cryptography Scheme for Securing Data in Cloud Computing","authors":"J. Athena, V. Sumathy","doi":"10.4236/CS.2017.83005","DOIUrl":"https://doi.org/10.4236/CS.2017.83005","url":null,"abstract":"Numerous advancements in the Information Technology (IT) require the proper security policy for the data storage and transfer among the cloud. With the increase in size of the data, the time required to handle the huge-size data is more. An assurance of security in cloud computing suffers various issues. The evolution of cryptographic approaches addresses these limitations and provides the solution to the data preserving. There are two issues in security assurance such as geographical distribution and the multi-tenancy of the cloud server. This paper surveys about the various cryptographic techniques with their key sizes, time required for key/signature generation and verification constraints. The survey discusses the architecture for secure data transmissions among the devices, challenges raised during the transmission and attacks. This paper presents the brief review of major cryptographic techniques such as Rivest, Shamir Adleman (RSA), Dffie Hellman and the Elliptic Curve Cryptography (ECC) associated key sizes. This paper investigates the general impact of digital signature generation techniques on cloud security with the advantages and disadvantages. The results and discussion section existing in this paper investigate the time consumption for key/signature generation and verification with the key size variations effectively. The initialization of random prime numbers and the key computation based on the points on the elliptic curve assures the high-security compared to the existing schemes with the minimum time consumption and sizes in cloud-based applications.","PeriodicalId":63422,"journal":{"name":"电路与系统(英文)","volume":"08 1","pages":"77-92"},"PeriodicalIF":0.0,"publicationDate":"2017-03-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49388074","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
电路与系统(英文)Pub Date : 2017-02-28DOI: 10.4236/CS.2017.82004
C. Rajasekaran, R. Jeyabharath, P. Veena
{"title":"FPGA SoC Based Multichannel Data Acquisition System with Network Control Module","authors":"C. Rajasekaran, R. Jeyabharath, P. Veena","doi":"10.4236/CS.2017.82004","DOIUrl":"https://doi.org/10.4236/CS.2017.82004","url":null,"abstract":"Normally, Data acquisition (DAQ) is used to acquire the signals from different devices like sensors, transducers, actuators etc. The data acquisition is also used to analyze the signals, digitizing the signals and acquiring the signals from different inputs. The main drawbacks in data acquisition system are data storage, hardware size and remote monitoring. The System-on-Chip Field Programmable Gate Array (SoC-FPGA) is used in the proposed system in the aim to reduce the hardware and memory size. Further to provide remote monitoring with Ethernet/Wi-Fi, the Network Control Module (NCM) is integrated with Data acquisition and processing module for the communication between the systems. This developed system achieves high resolution with memory reduction, reduced hardware size, fast remote monitoring and control. It is used for real time processing in DAQ and signal processing. For fault tolerance and portability, the full system reconfigurability based FPGA acts as the best solution and the system can be reused with different configurations. The control of data acquisition and the subsequent management of data are coded in LabVIEW. LabVIEW tool is used to design and develop a four-channel Data Acquisition and Processing (DAQP) unit. National Instruments Data Acquisition (NIDAQ) and National Instruments Field Programmable Gate Array (NIFPGA) are used to test and implement the design for real time processing. This is designed to provide high accuracy, storage and portability.","PeriodicalId":63422,"journal":{"name":"电路与系统(英文)","volume":"08 1","pages":"53-75"},"PeriodicalIF":0.0,"publicationDate":"2017-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"42298308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
电路与系统(英文)Pub Date : 2017-02-28DOI: 10.4236/CS.2017.82003
Pavankumar Bikki, P. Karuppanan
{"title":"SRAM Cell Leakage Control Techniques for Ultra Low Power Application: A Survey","authors":"Pavankumar Bikki, P. Karuppanan","doi":"10.4236/CS.2017.82003","DOIUrl":"https://doi.org/10.4236/CS.2017.82003","url":null,"abstract":"Low power supply operation with leakage power reduction is the prime concern in modern nano-scale CMOS memory devices. In the present scenario, low leakage memory architecture becomes more challenging, as it has 30% of the total chip power consumption. Since, the SRAM cell is low in density and most of memory processing data remain stable during the data holding operation, the stored memory data are more affected by the leakage phenomena in the circuit while the device parameters are scaled down. In this survey, origins of leakage currents in a short-channel device and various leakage control techniques for ultra-low power SRAM design are discussed. A classification of these approaches made based on their key design and functions, such as biasing technique, power gating and multi-threshold techniques. Based on our survey, we summarize the merits and demerits and challenges of these techniques. This comprehensive study will be helpful to extend the further research for future implementations.","PeriodicalId":63422,"journal":{"name":"电路与系统(英文)","volume":"08 1","pages":"720-726"},"PeriodicalIF":0.0,"publicationDate":"2017-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43648817","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
电路与系统(英文)Pub Date : 2017-01-10DOI: 10.4236/CS.2017.81001
K. Ohhata, K. Hotta, Naoto Yamaguchi, Daiki Hayakawa, Kenji Sewaki, Kento Imayanagida, Y. Sonoda
{"title":"A 500-MS/s, 2.0-mW, 8-Bit Subranging ADC with Time-Domain Quantizer","authors":"K. Ohhata, K. Hotta, Naoto Yamaguchi, Daiki Hayakawa, Kenji Sewaki, Kento Imayanagida, Y. Sonoda","doi":"10.4236/CS.2017.81001","DOIUrl":"https://doi.org/10.4236/CS.2017.81001","url":null,"abstract":"This paper describes a novel energy-efficient, high-speed ADC architecture combining a flash ADC and a TDC. A high conversion rate can be obtained owing to the flash coarse ADC, and low-power dissipation can be attained using the TDC as a fine ADC. Moreover, a capacitive coupled ramp circuit is proposed to achieve high linearity. A test chip was fabricated using 65-nm digital CMOS technology. The test chip demonstrated a high sampling frequency of 500 MHz and a low-power dissipation of 2.0 mW, resulting in a low FOM of 32 fJ/conversion-step.","PeriodicalId":63422,"journal":{"name":"电路与系统(英文)","volume":"08 1","pages":"1-13"},"PeriodicalIF":0.0,"publicationDate":"2017-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43910390","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
电路与系统(英文)Pub Date : 2017-01-10DOI: 10.4236/CS.2017.81002
K. L. Pushkar, G. Singh, R. Goel
{"title":"CMOS VDIBAs-Based Single-Resistance-Controlled Voltage-Mode Sinusoidal Oscillator","authors":"K. L. Pushkar, G. Singh, R. Goel","doi":"10.4236/CS.2017.81002","DOIUrl":"https://doi.org/10.4236/CS.2017.81002","url":null,"abstract":"In this communication, a new single-resistance controlled sinusoidal oscillator (SRCO) has been presented. The presented SRCO uses two voltage differencing inverting buffered amplifiers (VDIBAs), one resistor and two capacitors in which one is grounded (GC) and the other one is floating (FC). The proposed structure offers the following advantageous features: 1) independent control of oscillation condition (OC) and oscillation frequency (OF); 2) low passive and active sensitivities and 3) very good frequency stability. The non-ideal effects of the VDIBA on the proposed oscillator have also been investigated. The proposed SRCO has been tested for its robustness using Monte-Carlo simulations. The check of the validity of the presented SRCO has been established by SPICE simulations using 0.18 μm TSMC technology.","PeriodicalId":63422,"journal":{"name":"电路与系统(英文)","volume":" ","pages":"720-726"},"PeriodicalIF":0.0,"publicationDate":"2017-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"44529335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
电路与系统(英文)Pub Date : 2016-12-20DOI: 10.4236/CS.2016.714351
V. Shanthi, D. Somasundareswari
{"title":"An Efficient Coverage Greedy Packet Stateless Routing (EC-GPSR) in Authenties Based Wireless Sensor Networks","authors":"V. Shanthi, D. Somasundareswari","doi":"10.4236/CS.2016.714351","DOIUrl":"https://doi.org/10.4236/CS.2016.714351","url":null,"abstract":"A WSN (wireless sensor network) consists of lakhs of sensor nodes with low level energy, memory management, and computation routing capability. The real time world applications of WSN in some extreme perceive environment arrange sensor nodes complex to exchange once they use up the resource. Hence, lots of researchers in this field going towards on how to design a property routing protocol with extension route procedures to safety of transmission with prolong the life span of the network. The classical hybrid protocols such as LEACH and GPSR have better performance in saving the power consumption. However, the choosing formula eliminates the change of nodes’ Route will make the nodes acting as cluster heads too many times die of route with power early expressions to the consumption of too much Power and saves the route path. In this paper, we present WSN network route extension with supporting of cloud architecture of the state-of-the-art routing techniques in WSNs. Our Proposed Research belongs overcome of GPSR (Greedy Perimeter Stateless Routing) to EC-GPSR (Efficient Coverage-GPSR), ERA (Efficient Route Autonomous) and IC-GPSR (Isolated Coverage-GPSR) with solving of Route problems due to Route extension with help of cloud to store availability of routes and improve the scalability with compare AODV.","PeriodicalId":63422,"journal":{"name":"电路与系统(英文)","volume":"07 1","pages":"4291-4307"},"PeriodicalIF":0.0,"publicationDate":"2016-12-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"70468162","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
电路与系统(英文)Pub Date : 2016-12-20DOI: 10.4236/CS.2016.714352
S. Sridharan, S. Sudha
{"title":"High Frequency Charging Techniques—Grid Connected Power Generation Using Switched Reluctance Generator","authors":"S. Sridharan, S. Sudha","doi":"10.4236/CS.2016.714352","DOIUrl":"https://doi.org/10.4236/CS.2016.714352","url":null,"abstract":"Power generation becomes the need of developed, developing and under developed countries to meet their increasing power requirements. When affordability increases their requirement of power increases, this happens when increased per capita consumption. The existing power scenario states that highest power is produced using firing of coals called thermal energy. A high efficiency Switched Reluctance Generator (SRG) based high frequency switching scheme to enhance the output for grid connectivity is designed, fabricated and evaluated. This proposed method generates the output for the low wind speed. It provides output at low speed because of multi-level DC-DC converter and storage system. It is an efficient solution for low wind power generation. The real time readings and results are discussed.","PeriodicalId":63422,"journal":{"name":"电路与系统(英文)","volume":"07 1","pages":"4308-4321"},"PeriodicalIF":0.0,"publicationDate":"2016-12-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"70468232","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
电路与系统(英文)Pub Date : 2016-12-20DOI: 10.4236/CS.2016.714353
V. Velmurugan, Jeyabharath Rajaiah, Veena Parasunath
{"title":"Harmonic Minimization in Seven Level Cascaded Multilevel Inverter Using Selective Harmonic Elimination PWM Techniques","authors":"V. Velmurugan, Jeyabharath Rajaiah, Veena Parasunath","doi":"10.4236/CS.2016.714353","DOIUrl":"https://doi.org/10.4236/CS.2016.714353","url":null,"abstract":"This paper concentrates on enhancing the productivity of the multilevel inverter and nature of yield voltage waveform. Seven level lessened switches topology has been actualized with just seven switches. Essential Switching plan and Selective Harmonics Elimination were executed to diminish the Total Harmonics Distortion (THD) esteem. Selective Harmonics Elimination Stepped Waveform (SHESW) strategy is executed to dispense with the lower order harmonics. Fundamental switching plan is utilized to control the switches in the inverter. The proposed topology is reasonable for any number of levels. The harmonic lessening is accomplished by selecting fitting switching angles. It indicates would like to decrease starting expense and unpredictability consequently it is able for modern applications. In this paper, third and fifth level harmonics have been disposed of. Simulation work is done utilizing the MATLAB/Simulink programming results have been displayed to accept the hypothesis.","PeriodicalId":63422,"journal":{"name":"电路与系统(英文)","volume":"07 1","pages":"4322-4330"},"PeriodicalIF":0.0,"publicationDate":"2016-12-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"70468322","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
电路与系统(英文)Pub Date : 2016-11-11DOI: 10.4236/CS.2016.713337
A. Vasanthara, K. Krishnamoorthy
{"title":"Tire Pressure Monitoring System Using SoC and Low Power Design","authors":"A. Vasanthara, K. Krishnamoorthy","doi":"10.4236/CS.2016.713337","DOIUrl":"https://doi.org/10.4236/CS.2016.713337","url":null,"abstract":"This \u0000paper presents the tire pressure monitoring system (TPMS) by using the system \u0000on chip (SoC) mixed signals with the help of Bluetooth transmission and in \u0000advantage of low power consumption design. This is to monitor the variations in \u0000temperature and pressure of the vehicle’s tire, and the TPMS system is involved. It improves the driver’s \u0000safety by automatically detecting the tire pressure and temperature and then \u0000warning signal is sent to \u0000driver to take a measure, which prevents from accident. The proposed system of \u0000tire pressure monitoring system using SoC increases the speed of indication \u0000time to the driver by using mixed signals. The inflation of the tire can be \u0000avoided by preventing from high temperature and high pressure. Limitation of \u0000temperature and pressure in the previous system is also elongated i.e. temperature from 40℃ to 125℃ and pressure \u0000from 0 to 750 Kpa. Sensors, wireless communication (Bluetooth dongle) and SoC \u0000unit are used to design the low power TPMS. Quantitative results are taken and \u0000the analogy between temperature and pressure is also verified. The tested \u0000results proved by need of the practical system. Signal conditioning voltage and \u0000SoC unit is the trace for low power design TPMS. Finally, the performance of \u0000the system is tested and executed by using proteus software given as a real \u0000time application.","PeriodicalId":63422,"journal":{"name":"电路与系统(英文)","volume":"07 1","pages":"4085-4097"},"PeriodicalIF":0.0,"publicationDate":"2016-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"70467576","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
电路与系统(英文)Pub Date : 2016-11-11DOI: 10.4236/CS.2016.713350
T. S. B. Damodhar, A. Kumar
{"title":"Implementation of FPGA Based Hybrid Power Generator for PV and Wind Grid Applications","authors":"T. S. B. Damodhar, A. Kumar","doi":"10.4236/CS.2016.713350","DOIUrl":"https://doi.org/10.4236/CS.2016.713350","url":null,"abstract":"This paper deals with implementation of Sinusoidal Pulse-Width-Modulation (SPWM) for a single-phase hybrid power filter generator for Photovoltaic (PV) and wind grid applications. Using policy iteration algorithm, an improved variable step-size perturbation and observation algorithm is contrived and it is implemented proficiently using a hard-ware description language (VHDL) (Very High Speed Integrated Circuit Hardware Description Language). Subsequently, the new generated grid source supplements the existing grid power in rural houses during its cut off or restricted supply period. The software is used for generating SPWM modulation integrated with a solar-power & wind power grid system which is implemented on the Spartan 3 FPGA. The proposed algorithm performs as a conventional controller in terms of tracking speed and mitigating fluctuation output power in steady state operation which is shown in the experimental results with a commercial PV array and HPW (Height Weight Proportional) show. Simulation results demonstrate the validity with load of the proposed algorithm.","PeriodicalId":63422,"journal":{"name":"电路与系统(英文)","volume":"07 1","pages":"4280-4290"},"PeriodicalIF":0.0,"publicationDate":"2016-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"70468528","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}