一种带时域量化器的500-MS/s、2.0-mW、8位子范围ADC

电路与系统(英文) Pub Date : 2017-01-10 DOI:10.4236/CS.2017.81001

K. Ohhata, K. Hotta, Naoto Yamaguchi, Daiki Hayakawa, Kenji Sewaki, Kento Imayanagida, Y. Sonoda

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引用次数: 3

摘要

本文描述了一种新的节能、高速ADC架构，该架构结合了闪存ADC和TDC。由于闪速粗略ADC可以获得高转换率，并且使用TDC作为精细ADC可以获得低功耗。此外，提出了一种电容耦合斜坡电路以实现高线性度。采用65nm数字CMOS技术制作了测试芯片。测试芯片显示出500 MHz的高采样频率和2.0 mW的低功耗，从而产生32 fJ/转换步长的低FOM。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A 500-MS/s, 2.0-mW, 8-Bit Subranging ADC with Time-Domain Quantizer

This paper describes a novel energy-efficient, high-speed ADC architecture combining a flash ADC and a TDC. A high conversion rate can be obtained owing to the flash coarse ADC, and low-power dissipation can be attained using the TDC as a fine ADC. Moreover, a capacitive coupled ramp circuit is proposed to achieve high linearity. A test chip was fabricated using 65-nm digital CMOS technology. The test chip demonstrated a high sampling frequency of 500 MHz and a low-power dissipation of 2.0 mW, resulting in a low FOM of 32 fJ/conversion-step.

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来源期刊

电路与系统(英文)

自引率

0.00%

发文量

273