A High Performance and Energy Efficient Microprocessor with a Novel Restricted Dynamically Reconfigurable Accelerator

Itaru Hida, Shinya Takamaeda-Yamazaki, M. Ikebe, M. Motomura, T. Asai
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引用次数: 4

Abstract

In the era of Internet of Things, the battery life of edge devices must be extended for sensing connection to the Internet. We aim to reduce the power consumption of the microprocessor embedded in such devices by using a novel dynamically reconfigurable accelerator. Conventional microprocessors consume a large amount of power for memory access, in registers, and for the control of the processor itself rather than computation; this decreases the energy efficiency. Dynamically reconfigurable accelerators reduce such redundant power by computing in parallel on reconfigurable switches and processing element arrays (often consisting of an arithmetic logic unit (ALU) and registers). We propose a novel dynamically reconfigurable accelerator “DYNaSTA” composed of a dynamically reconfigurable data path and static ALU arrays. The static ALU arrays process instructions in parallel without registers and improve energy efficiency. The dynamically reconfigurable data path includes registers and many switches dynamically reconfigured to resolve operand dependencies between instructions mapped on the static ALU array, and forwards appropriate operands to the static ALU array. Therefore, the DYNaSTA accelerator has more flexibility while improving the energy efficiency compared with the conventional dynamically reconfigurable accelerators. We simulated the power consumption of the proposed DYNaSTA accelerator and measured the fabricated chip. As a result, the power consumption was reduced by 69% to 86%, and the energy efficiency improved 4.5 to 13 times compared to a general RISC microprocessor.
一种具有新型受限动态可重构加速器的高性能节能微处理器
在物联网时代,边缘设备的电池寿命必须延长,才能感应连接到互联网。我们的目标是通过使用一种新颖的动态可重构加速器来降低嵌入在此类器件中的微处理器的功耗。传统的微处理器在内存访问、寄存器和处理器本身的控制上消耗大量的能量,而不是计算;这降低了能源效率。动态可重构加速器通过并行计算可重构开关和处理元素阵列(通常由算术逻辑单元(ALU)和寄存器组成)来减少冗余功率。本文提出了一种由动态可重构数据路径和静态ALU阵列组成的新型动态可重构加速器“DYNaSTA”。静态ALU阵列在没有寄存器的情况下并行处理指令,提高了能效。动态可重新配置的数据路径包括寄存器和许多动态重新配置的开关,以解决映射到静态ALU数组上的指令之间的操作数依赖关系,并将适当的操作数转发给静态ALU数组。因此,与传统的动态可重构加速器相比,DYNaSTA加速器在提高能效的同时具有更大的灵活性。我们模拟了所提出的DYNaSTA加速器的功耗,并测量了制作的芯片。因此,功耗降低了69%到86%,能源效率比普通RISC微处理器提高了4.5到13倍。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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