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A New Current Conveyor Full-Wave Rectifier for Low Frequency/Small Signal Medical Applications 一种低频/小信号医用新型电流输送全波整流器
电路与系统(英文) Pub Date : 2018-03-15 DOI: 10.4236/CS.2018.93006
A. Monpapassorn
{"title":"A New Current Conveyor Full-Wave Rectifier for Low Frequency/Small Signal Medical Applications","authors":"A. Monpapassorn","doi":"10.4236/CS.2018.93006","DOIUrl":"https://doi.org/10.4236/CS.2018.93006","url":null,"abstract":"This paper presents a new current conveyor (CCII+) full-wave rectifier for low frequency/small signal medical applications. The proposed rectifier is based on the current conveyor full-wave rectifier proposed previously, but the proposed rectifier is better in view of no need diodes to rectify, and no need bias sources to overcome the zero crossing error. It needs only two CCII+s, two resistors, and three simple current mirrors, which is easy for IC implementation and for building in many countries. The PSPICE simulation with the current conveyor CCII+ in the current feedback opamp AD844 IC and the 2N2222 bipolar current mirror shows the good low frequency/small signal rectification, the operation voltage of down to 6 .","PeriodicalId":63422,"journal":{"name":"电路与系统(英文)","volume":"9 1","pages":"58-65"},"PeriodicalIF":0.0,"publicationDate":"2018-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"44240162","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Electronically Controllable Quadrature Sinusoidal Oscillator Using VD-DIBAs 采用VD DIBA的电子可控正交正弦振荡器
电路与系统(英文) Pub Date : 2018-03-15 DOI: 10.4236/CS.2018.93004
K. L. Pushkar
{"title":"Electronically Controllable Quadrature Sinusoidal Oscillator Using VD-DIBAs","authors":"K. L. Pushkar","doi":"10.4236/CS.2018.93004","DOIUrl":"https://doi.org/10.4236/CS.2018.93004","url":null,"abstract":"A new voltage-mode quadrature sinusoidal oscillator (QSO) using two voltage differencing-differential input buffered amplifiers (VD-DIBAs) and only three passive components (two capacitors and a resistor) is presented. The proposed QSO circuit offers advantages of independent electronic control of both oscillation frequency and condition of oscillation, availability of two quadrature voltage outputs and low active and passive sensitivities. SPICE simulation results have been included using 0.35 μm MIETEC technology to confirm the validity of the proposed QSO oscillator.","PeriodicalId":63422,"journal":{"name":"电路与系统(英文)","volume":"09 1","pages":"41-48"},"PeriodicalIF":0.0,"publicationDate":"2018-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"42643059","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Design of Digital to Analog Converters with Arbitrary Radix 任意基数模转换器的设计
电路与系统(英文) Pub Date : 2018-03-15 DOI: 10.4236/CS.2018.93005
T. Rathore
{"title":"Design of Digital to Analog Converters with Arbitrary Radix","authors":"T. Rathore","doi":"10.4236/CS.2018.93005","DOIUrl":"https://doi.org/10.4236/CS.2018.93005","url":null,"abstract":"There are DAC structures available in the literature for radix r = 2, 3, and 4; but how they are arrived at is missing. No general structure is available for any radix r. The aim of the paper is, therefore, to fulfil these gaps. To start with, the design relations are derived for the simplest possible attenuator circuit when connected to a voltage source V and a series resistance R, such that the complete circuit offers the Thevenin resistance R. Spread relations for this attenuator are derived. An example when 3 such attenuators with different attenuation constants are connected in cascade is given. Interestingly, the two attenuators with attenuation factors 1/2 and 1/3 have the same spread of 2. A generalized attenuator is then obtained when N number of identical attenuators are connected in cascade. This is modified to derive a digital to analog converter for any radix r.","PeriodicalId":63422,"journal":{"name":"电路与系统(英文)","volume":"09 1","pages":"49-57"},"PeriodicalIF":0.0,"publicationDate":"2018-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"42585831","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Development of a Solar Controller with MLI Control MLI控制太阳能控制器的研制
电路与系统(英文) Pub Date : 2018-02-08 DOI: 10.4236/CS.2018.92003
M. Wade, Moussa Gueye, Ousmane Sow, Daouda Sow, Babou Dione, G. Sissoko
{"title":"Development of a Solar Controller with MLI Control","authors":"M. Wade, Moussa Gueye, Ousmane Sow, Daouda Sow, Babou Dione, G. Sissoko","doi":"10.4236/CS.2018.92003","DOIUrl":"https://doi.org/10.4236/CS.2018.92003","url":null,"abstract":"This work presents the development of a solar regulator which manages the charge and discharge of a (lead) battery installed in a photovoltaic system in order to extend its lifetime. The regulator is controlled by a microcontroller (PIC16F877A) and protects the battery against overcharging, deep discharge, but also against temperature drifts. The operating principle is based on the control of a DC-DC converter by a rectangular signal MLI generated by the microcontroller. In addition to the protection function of the regulator, there is included a control and monitoring panel consisting of a visualization interface on which the system quantities can be observed. Thus, it will be given to the user to be able to act on the system. This display interface uses as a display an LCD screen and LEDs. Simulation results are presented to illustrate the operation of the proposed solar controller.","PeriodicalId":63422,"journal":{"name":"电路与系统(英文)","volume":"09 1","pages":"22-40"},"PeriodicalIF":0.0,"publicationDate":"2018-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"47008590","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Review of the Global Trend of Interconnect Reliability for Integrated Circuit 集成电路互连可靠性全球发展趋势综述
电路与系统(英文) Pub Date : 2018-02-08 DOI: 10.4236/CS.2018.92002
Q. Lin, Haifeng Wu, Guoqing Jia
{"title":"Review of the Global Trend of Interconnect Reliability for Integrated Circuit","authors":"Q. Lin, Haifeng Wu, Guoqing Jia","doi":"10.4236/CS.2018.92002","DOIUrl":"https://doi.org/10.4236/CS.2018.92002","url":null,"abstract":"Interconnect reliability has been regarded as a discipline that must be seriously taken into account from the early design phase of integrated circuit (IC). In order to study the status and trend of the interconnect reliability, a comprehensive review of the published literatures is carried out. This can depict the global trend of ICs’ interconnect reliability and help the new entrants to understand the present situation of this area.","PeriodicalId":63422,"journal":{"name":"电路与系统(英文)","volume":"09 1","pages":"9-21"},"PeriodicalIF":0.0,"publicationDate":"2018-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"41750615","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Single-Resistance Controlled Sinusoidal Oscillator Employing Single Universal Voltage Conveyor 采用单通用电压传送器的单电阻控制正弦振荡器
电路与系统(英文) Pub Date : 2018-01-25 DOI: 10.4236/CS.2018.91001
K. L. Pushkar
{"title":"Single-Resistance Controlled Sinusoidal Oscillator Employing Single Universal Voltage Conveyor","authors":"K. L. Pushkar","doi":"10.4236/CS.2018.91001","DOIUrl":"https://doi.org/10.4236/CS.2018.91001","url":null,"abstract":"In this paper, a new single-resistance controlled sinusoidal oscillator (SRCO) using single universal voltage conveyor (UVC) has been presented. The proposed SRCO employs single universal voltage conveyor, three resistors, and two capacitors. The proposed configuration offers the following advantageous features (1) independent control of condition of oscillation and frequency of oscillation (2) low passive sensitivities. The validity of the proposed SRCO has been established by SPICE (version 16.5) simulations using Taiwan Semiconductor Manufacturing Company (TSMC) 0.18 μm technology.","PeriodicalId":63422,"journal":{"name":"电路与系统(英文)","volume":"09 1","pages":"1-7"},"PeriodicalIF":0.0,"publicationDate":"2018-01-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"46713130","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A New Voltage-Mode Universal Biquadratic Filter Using Single UVC 一种新型电压型通用双二次型单UVC滤波器
电路与系统(英文) Pub Date : 2017-12-27 DOI: 10.4236/CS.2017.812020
K. L. Pushkar, Kavya Gupta, Pinky Vivek
{"title":"A New Voltage-Mode Universal Biquadratic Filter Using Single UVC","authors":"K. L. Pushkar, Kavya Gupta, Pinky Vivek","doi":"10.4236/CS.2017.812020","DOIUrl":"https://doi.org/10.4236/CS.2017.812020","url":null,"abstract":"The paper presents a new universal biquadratic filter using single universal voltage conveyor (UVC), two resistors and two capacitors. The offered structure has three inputs and one output and can realise all the five basic biquadratic filters: high-pass (HP), low-pass (LP), band-reject (BR), band-pass (BP) and all-pass (AP) from the same circuit topology. The proposed universal filter also provides following advantageous features, not available simultaneously in any UVC based universal biquadratic filter so far: (i) low active and passive sensitivities, (ii) independent control of natural frequency (ω0) and bandwidth (BW) and (iii) no requirement of any component matching condition and inversion of input signal(s) (as needed in most of the earlier reported structures). The workability of proposed structure has been presented by SPICE (Version 16.5) simulation using 0.18 μm TSMC technology.","PeriodicalId":63422,"journal":{"name":"电路与系统(英文)","volume":"08 1","pages":"275-284"},"PeriodicalIF":0.0,"publicationDate":"2017-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"44156183","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Efficient VLSI Implementation of the C-MANTEC Conn Algorithm by Using PID Controllers 用PID控制器实现C-MANTEC Conn算法的高效VLSI实现
电路与系统(英文) Pub Date : 2017-11-03 DOI: 10.4236/CS.2017.811018
J. Caleb, M. Kannan
{"title":"Efficient VLSI Implementation of the C-MANTEC Conn Algorithm by Using PID Controllers","authors":"J. Caleb, M. Kannan","doi":"10.4236/CS.2017.811018","DOIUrl":"https://doi.org/10.4236/CS.2017.811018","url":null,"abstract":"Through the research on the existing C-MANTEC neural network and PID control technology, this paper presents an improved C-MANTEC algorithm based on PID control system. The combining of the artificial neural networks with conventional PID control helps in exploring their respective advantages to forming the intelligent PID control. From UCI Repository cancer dataset, the developed system is tested. The results show that the scheme can not only improve the speed of the algorithm in the training process but also improve the generalization capability of the network, which further enhances the performance of PID controllers. The overall power consumed is also reduced to a greater extent.","PeriodicalId":63422,"journal":{"name":"电路与系统(英文)","volume":"08 1","pages":"253-260"},"PeriodicalIF":0.0,"publicationDate":"2017-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"44811627","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Analysis of Electronic Circuits with the Signal Flow Graph Method 用信号流图法分析电子电路
电路与系统(英文) Pub Date : 2017-11-03 DOI: 10.4236/CS.2017.811019
Feim Ridvan Rasim, S. Sattler
{"title":"Analysis of Electronic Circuits with the Signal Flow Graph Method","authors":"Feim Ridvan Rasim, S. Sattler","doi":"10.4236/CS.2017.811019","DOIUrl":"https://doi.org/10.4236/CS.2017.811019","url":null,"abstract":"In this work a method called “signal flow graph (SFG)” is presented. A signal-flow graph describes a system by its signal flow by directed and weighted graph; the signals are applied to nodes and functions on edges. The edges of the signal flow graph are small processing units, through which the incoming signals are processed in a certain form. In this case, the result is sent to the outgoing node. The SFG allows a good visual inspection into complex feedback problems. Furthermore such a presentation allows for a clear and unambiguous description of a generating system, for example, a netview. A Signal Flow Graph (SFG) allows a fast and practical network analysis based on a clear data presentation in graphic format of the mathematical linear equations of the circuit. During creation of a SFG the Direct Current-Case (DC-Case) was observed since the correct current and voltage directions was drawn from zero frequency. In addition, the mathematical axioms, which are based on field algebra, are declared. In this work we show you in addition: How we check our SFG whether it is a consistent system or not. A signal flow graph can be verified by generating the identity of the signal flow graph itself, illustrated by the inverse signal flow graph (SFG−1). Two signal flow graphs are always generated from one circuit, so that the signal flow diagram already presented in previous sections corresponds to only half of the solution. The other half of the solution is the so-called identity, which represents the (SFG−1). If these two graphs are superposed with one another, so called 1-edges are created at the node points. In Boolean algebra, these 1-edges are given the value 1, whereas this value can be identified with a zero in the field algebra.","PeriodicalId":63422,"journal":{"name":"电路与系统(英文)","volume":"08 1","pages":"261-274"},"PeriodicalIF":0.0,"publicationDate":"2017-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"48783384","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Error Analysis of Approximate Calculation of Voltage Divider Biased Common-Emitter Amplifier 分压器偏置共发射极放大器近似计算的误差分析
电路与系统(英文) Pub Date : 2017-10-17 DOI: 10.4236/CS.2017.810017
Xinwu Chen, Jingjing Xue, Shuangbo Xie, W. Huang, Peng Wang, Ke Gong, Lijuan Zhong
{"title":"Error Analysis of Approximate Calculation of Voltage Divider Biased Common-Emitter Amplifier","authors":"Xinwu Chen, Jingjing Xue, Shuangbo Xie, W. Huang, Peng Wang, Ke Gong, Lijuan Zhong","doi":"10.4236/CS.2017.810017","DOIUrl":"https://doi.org/10.4236/CS.2017.810017","url":null,"abstract":"Voltage divider biasing common emitter amplifier is one of the core contents in analog circuit curriculum, and almost all of traditional textbooks apply approximate calculation method to estimate all characteristic parameters. In calculating quiescent point, transistor base current is generally ignored to get the approximate base potential and emitter current, then other operating parameters, and AC small signal parameters can be acquired. The main purpose of this paper is to compare traditional and Thevenin equivalent methods and to get the difference of the two methods. A Formula is given to calculate the error of the traditional method. Example calculating reveals that the traditional method can generate an error about 10%, and even severe for small signal amplifier with higher quiescent point.","PeriodicalId":63422,"journal":{"name":"电路与系统(英文)","volume":"08 1","pages":"247-252"},"PeriodicalIF":0.0,"publicationDate":"2017-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"46872207","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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