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Realizations of Voltage Transfer Functions Using DVCCs 用dvcc实现电压传递函数
电路与系统(英文) Pub Date : 2018-10-31 DOI: 10.4236/CS.2018.910015
T. Rathore
{"title":"Realizations of Voltage Transfer Functions Using DVCCs","authors":"T. Rathore","doi":"10.4236/CS.2018.910015","DOIUrl":"https://doi.org/10.4236/CS.2018.910015","url":null,"abstract":"Maheshwari has proposed three differential-voltage current-conveyor configurations for realizing first order all-pass filters only. This paper has exploited these configurations for realizing more complex transfer function T(s) which yield poles and zeros of 1 - T(s) in one of the four admissible patterns. Bilinear and biquadratic functions are dealt in detail. It is shown that only bilinear functions can be realized with all the four passive elements grounded. First order all-pass function is a special case which needs only three elements (2R, 1C) or (1R, 2C). A biquadratic function requires (2R, 2C) elements and has all the capacitor grounded. Design of second order all-pass function is given.","PeriodicalId":63422,"journal":{"name":"电路与系统(英文)","volume":"09 1","pages":"141-147"},"PeriodicalIF":0.0,"publicationDate":"2018-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43333277","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Peak Detection Implementation for Real-Time Signal Analysis Based on FPGA 基于FPGA的实时信号分析峰值检测实现
电路与系统(英文) Pub Date : 2018-10-31 DOI: 10.4236/CS.2018.910016
A. Çolak, Taito Manabe, Y. Shibata, F. Kurokawa
{"title":"Peak Detection Implementation for Real-Time Signal Analysis Based on FPGA","authors":"A. Çolak, Taito Manabe, Y. Shibata, F. Kurokawa","doi":"10.4236/CS.2018.910016","DOIUrl":"https://doi.org/10.4236/CS.2018.910016","url":null,"abstract":"In this paper a real-time peak detection method based on modified Automatic Multiscale Field Detection (AMPD) algorithm and Field Programmable Gate Arrays (FPGA) technologies of a time series data is studied, and optimum scaling is highlighted after testing several scales. To validate the results obtained from modified algorithm, they are compared with the results of original AMPD method. As data of this study, three-phase voltage values of a power station are used. A detail detective sensitivity analysis of phase-to-phase voltage values is tried at different scales. Moreover, the original algorithm is tested regarding the off-line mode to obtain optimum scaling for real-time peak point detection. It is concluded that the peak detection of minimum and maximum points of data series achieved by modified algorithm is very close to the results of original AMPD algorithm.","PeriodicalId":63422,"journal":{"name":"电路与系统(英文)","volume":"09 1","pages":"148-167"},"PeriodicalIF":0.0,"publicationDate":"2018-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"47807201","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
CM-Biquad Filter Using Single DO-VDBA 使用单个DO-VDBA的CM双四元滤波器
电路与系统(英文) Pub Date : 2018-09-13 DOI: 10.4236/CS.2018.99014
Chandra Ketu Yadav, D. Prasad, Zainab Haseeb, Laxya, Mayank Kumar
{"title":"CM-Biquad Filter Using Single DO-VDBA","authors":"Chandra Ketu Yadav, D. Prasad, Zainab Haseeb, Laxya, Mayank Kumar","doi":"10.4236/CS.2018.99014","DOIUrl":"https://doi.org/10.4236/CS.2018.99014","url":null,"abstract":"In this manuscript we present a current mode biquad using one dual output-voltage differencing buffered amplifier (DO-VDBA) and four passive components (2 grounded capacitors and 2 resistors). The proposed circuit offers very low active and passive sensitivity. The filter presented here is electronically tunable, frequency of oscillation (FO) can be tuned by controlling transconductance (gm) by varying the bias current (IB) of the circuit. The workability of proposed circuit is tested using PSPICE with 180 nm TSMC CMOS process parameters.","PeriodicalId":63422,"journal":{"name":"电路与系统(英文)","volume":"09 1","pages":"133-139"},"PeriodicalIF":0.0,"publicationDate":"2018-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"47216981","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Design of High-Utilization Current-Sharing Controller for Battery-Ultracapacitor Hybrid Energy Storage System 电池-超电容混合储能系统高利用率均流控制器的设计
电路与系统(英文) Pub Date : 2018-09-13 DOI: 10.4236/CS.2018.99013
Lan-Rong Dung, Zhenghuang Lin
{"title":"Design of High-Utilization Current-Sharing Controller for Battery-Ultracapacitor Hybrid Energy Storage System","authors":"Lan-Rong Dung, Zhenghuang Lin","doi":"10.4236/CS.2018.99013","DOIUrl":"https://doi.org/10.4236/CS.2018.99013","url":null,"abstract":"In this paper, a new control strategy of battery-ultracapacitor hybrid energy storage system (HESS) is proposed for hybrid electric drive vehicles (HEVs). Compared to the stand, alone battery system may not be sufficient to satisfy peak demand periods during transients in HEVs, the ultracapacitor pack can supply or recover the peak power and it can be used in high C-rates. However, the problem of battery-ultracapacitor hybrid energy storage system (HESS) is how to interconnect the battery and ultracapacitor and how to control the power distribution. This paper reviewed some battery-ultracapacitor hybrid energy storage system topology and investigated the advantages and disadvantages, then proposed a new control strategy. The proposed control strategy can improve the system performance and ultracapacitor utilization, while also decreasing the battery pack size to avoid the thermal runaway problems and increase the life of the battery. The experiment results showed the proposed control strategy can improve 3% - 4% ultracapacitor utilization.","PeriodicalId":63422,"journal":{"name":"电路与系统(英文)","volume":"09 1","pages":"125-132"},"PeriodicalIF":0.0,"publicationDate":"2018-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"46081648","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
New Current Mode Lossy Integrator Employing CDDITA 基于cdddita的新型电流模式有损积分器
电路与系统(英文) Pub Date : 2018-08-13 DOI: 10.4236/CS.2018.98012
K. Panwar, D. Prasad, M. Srivastava, Zainab Haseeb
{"title":"New Current Mode Lossy Integrator Employing CDDITA","authors":"K. Panwar, D. Prasad, M. Srivastava, Zainab Haseeb","doi":"10.4236/CS.2018.98012","DOIUrl":"https://doi.org/10.4236/CS.2018.98012","url":null,"abstract":"This work presents a novel current-mode (CM) lossless integrator that uses one current differencing differential input transconductance amplifier (CDDITA) and one grounded capacitor. The configuration based on single active element has several advantages from the aspect of monolithic integration, few are: reduced power consumption, chip miniaturization. Employment of grounded capacitor is also beneficial for monolithic integration. Specifying some of the key features of integrator proposed are: 1) purely resistorless, 2) electronically tunable, 3) current output available at the port having high impedance, and 4) excellent performance under non-ideal conditions. So, a resister-less current mode lossy integrator with electronic control employing single CDDITA has been proposed in this paper. The verification of workability of the proposed current mode integrator is well explained by the help of SPICE simulations using TSMC CMOS 0.18 μm technology node.","PeriodicalId":63422,"journal":{"name":"电路与系统(英文)","volume":"09 1","pages":"117-123"},"PeriodicalIF":0.0,"publicationDate":"2018-08-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"46394177","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
The Effect and Compensation of Phase Noise on Orthogonal Frequency Division Multiplexing (OFDM) System 相位噪声对正交频分复用（OFDM）系统的影响及补偿
电路与系统(英文) Pub Date : 2018-07-23 DOI: 10.4236/CS.2018.97011
Yubin Lin
{"title":"The Effect and Compensation of Phase Noise on Orthogonal Frequency Division Multiplexing (OFDM) System","authors":"Yubin Lin","doi":"10.4236/CS.2018.97011","DOIUrl":"https://doi.org/10.4236/CS.2018.97011","url":null,"abstract":"Orthogonal Frequency Division Multiplexing (OFDM) is characterized by its high data rate. However, the modulation method used in the system is subject to the influence of phase noise due to the need of time synchronization. In this paper, an algorithm based on MMSE (minimum mean square error) is developed to compensate the influence of both the common phase error (CPE) and inter carrier interference (ICI), which are two aspects of phase noise, under common Gaussian white noise. The result of noise cancellation is presented in signal-to-noise ratio (SNR) and symbol error rate (SER). Like digital signal in general, SNR can reduce SER with or without phase noise compensation. The compensation of phase noise significantly reduces the SER of the decoded signal. However, the bandwidth of phase noise still determines the signal accuracy. Under high bandwidth of phase noise, increasing SNR will only slightly increase SER, which is not efficient.","PeriodicalId":63422,"journal":{"name":"电路与系统(英文)","volume":"9 1","pages":"107-115"},"PeriodicalIF":0.0,"publicationDate":"2018-07-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43029008","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Optimization of a Si-SiO2 Waveguide Coupler for Photonic Integrated Circuits 用于光子集成电路的Si-SiO2波导耦合器的优化
电路与系统(英文) Pub Date : 2018-07-23 DOI: 10.4236/CS.2018.97010
Yike Wang
{"title":"Optimization of a Si-SiO2 Waveguide Coupler for Photonic Integrated Circuits","authors":"Yike Wang","doi":"10.4236/CS.2018.97010","DOIUrl":"https://doi.org/10.4236/CS.2018.97010","url":null,"abstract":"In this paper, we demonstrated a compact Si-SiO2 waveguide coupler with a footprint of only 2 μm × 3 μm by topology optimization in the communication wavelength. The transmission was increased from 30% to 100%, much higher than other methods. Besides, the optimized structure did not incorporate other dielectric materials, facilitating fabrications and applications.","PeriodicalId":63422,"journal":{"name":"电路与系统(英文)","volume":"09 1","pages":"101-106"},"PeriodicalIF":0.0,"publicationDate":"2018-07-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"46144637","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Efficient Realization of Vinculum Vedic BCD Multipliers for High Speed Applications 高速应用的真空吠陀BCD乘法器的高效实现
电路与系统(英文) Pub Date : 2018-06-29 DOI: 10.4236/CS.2018.96009
G. Sreelakshmi, K. Fatima, B. Madhavi
{"title":"Efficient Realization of Vinculum Vedic BCD Multipliers for High Speed Applications","authors":"G. Sreelakshmi, K. Fatima, B. Madhavi","doi":"10.4236/CS.2018.96009","DOIUrl":"https://doi.org/10.4236/CS.2018.96009","url":null,"abstract":"Decimal multipliers play an important role in our day to day life for commercial, financial and tax applications. Every processor multiplier acts as the basic building block which decides the performance of processor. Time and again research is going on to design high-performance, low-latency BCD multiplier architectures. This paper proposes a new approach to BCD multiplication using vinculum number system. The key feature of the proposed architecture uses entirely a new one digit ROM based BCD multiplier that uses vinculum numbers as operands. Using this one digit BCD multiplier, an N digit BCD multiplier is built by using the vedic vertical cross wire method (Urdhav Triyagbhyam). We have also used our proposed multi operand VBCD Adder (Vinculum BCD Adder) [my paper 26] to add the partial products. In this paper, we show that this approach is a promising alternative to conventional BCD multiplication or other decimal multiplication methods that use alternative decimal representations like 5211, 4221, Xs3 etc.","PeriodicalId":63422,"journal":{"name":"电路与系统(英文)","volume":"09 1","pages":"87-99"},"PeriodicalIF":0.0,"publicationDate":"2018-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"41773991","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Discharge Characteristics of a Triple-Well Diode-String ESD Clamp 三孔二极管串式ESD钳位的放电特性
电路与系统(英文) Pub Date : 2018-05-31 DOI: 10.4236/cs.2018.95008
J. Choi
{"title":"Discharge Characteristics of a Triple-Well Diode-String ESD Clamp","authors":"J. Choi","doi":"10.4236/cs.2018.95008","DOIUrl":"https://doi.org/10.4236/cs.2018.95008","url":null,"abstract":"In this work, DC and transient characteristics of a 4 diode string utilizing triple-well technologies as a VDD-VSS clamp device for ESD protection are analyzed in detail based on 2-dimensional device and mixed-mode simulations. It is shown that there exists parasitic pnp bipolar transistor action in this device leading to a sudden increase in DC substrate leakage if anode bias is getting high. Through transient simulations for a 2000 V PS-mode HBM ESD discharge event, it is shown that the dominant discharge path is the one formed by a parasitic pnpn thyristor and a parasitic npn bipolar transistor in series. Percentage ratios of the various current components regarding the anode current at its current peaking are provided. The mechanisms involved in ESD discharge inside the diode-string clamp utilizing triple-well technologies are explained in detail, which has never been done anywhere in the literature based on simulations or measurements.","PeriodicalId":63422,"journal":{"name":"电路与系统(英文)","volume":" 22","pages":"75-86"},"PeriodicalIF":0.0,"publicationDate":"2018-05-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"41311149","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Design of a Low-Cost Underwater LED Fishing Light Attractor 一种低成本的水下LED鱼灯吸引器的设计
电路与系统(英文) Pub Date : 2018-04-23 DOI: 10.4236/CS.2018.94007
Geophrey Telemka, Mariana Mghamba, Amos Vincent Ntarisa
{"title":"Design of a Low-Cost Underwater LED Fishing Light Attractor","authors":"Geophrey Telemka, Mariana Mghamba, Amos Vincent Ntarisa","doi":"10.4236/CS.2018.94007","DOIUrl":"https://doi.org/10.4236/CS.2018.94007","url":null,"abstract":"Fishermen generally use light as a common way to attract fish in the fishing industry. This study aimed to design a model of an underwater fishing using Light Emitting Diode (LED) lamp which is less costful and suitable for fishermen of Tanzania. Most fishermen currently use kerosene based lamps like candela which consumes lots of energy leading to high cost in terms of money used to regenerate the energy. This running cost automatically rises up the price of fish in the market. Thus with the use of LED lamp the cost will be reduced. The findings from this study showed that the LED lamp consumes little amount of energy (energy saving) compared to candela lamp which consumes 6 liters of kerosene per 36 hours which is equivalent to three nights, while the LED lamp takes 7 batteries at once for 36 hours. The 6 liters of kerosene cost around 7 USD and that of 7 batteries cost is near 2 USD. The LED lamp can be accessed by only 15 USD the price which is nearly half the price of the candela lamp. The candela lamp in the market is sold around 31 USD. This shows that LED lamp is more efficient in terms of conserving energy and cost effective than candela lamp. It is recommended that fishermen in the fishing industry in Tanzania should employ the usage of underwater LED fishing lamps as they are energy efficient. This will help the fishermen of Tanzania to undertake the fishing activity at low cost which will result to the decrease of price of fish in the market. This shows that this LED lamp has high efficiency and effectiveness to be used by fishermen compared to traditional method used by majority of them.","PeriodicalId":63422,"journal":{"name":"电路与系统(英文)","volume":"9 1","pages":"67-73"},"PeriodicalIF":0.0,"publicationDate":"2018-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"48113693","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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