三孔二极管串式ESD钳位的放电特性

J. Choi
{"title":"三孔二极管串式ESD钳位的放电特性","authors":"J. Choi","doi":"10.4236/cs.2018.95008","DOIUrl":null,"url":null,"abstract":"In this work, DC and transient characteristics of a 4 diode string utilizing triple-well technologies as a VDD-VSS clamp device for ESD protection are analyzed in detail based on 2-dimensional device and mixed-mode simulations. It is shown that there exists parasitic pnp bipolar transistor action in this device leading to a sudden increase in DC substrate leakage if anode bias is getting high. Through transient simulations for a 2000 V PS-mode HBM ESD discharge event, it is shown that the dominant discharge path is the one formed by a parasitic pnpn thyristor and a parasitic npn bipolar transistor in series. Percentage ratios of the various current components regarding the anode current at its current peaking are provided. The mechanisms involved in ESD discharge inside the diode-string clamp utilizing triple-well technologies are explained in detail, which has never been done anywhere in the literature based on simulations or measurements.","PeriodicalId":63422,"journal":{"name":"电路与系统(英文)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2018-05-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Discharge Characteristics of a Triple-Well Diode-String ESD Clamp\",\"authors\":\"J. Choi\",\"doi\":\"10.4236/cs.2018.95008\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this work, DC and transient characteristics of a 4 diode string utilizing triple-well technologies as a VDD-VSS clamp device for ESD protection are analyzed in detail based on 2-dimensional device and mixed-mode simulations. It is shown that there exists parasitic pnp bipolar transistor action in this device leading to a sudden increase in DC substrate leakage if anode bias is getting high. Through transient simulations for a 2000 V PS-mode HBM ESD discharge event, it is shown that the dominant discharge path is the one formed by a parasitic pnpn thyristor and a parasitic npn bipolar transistor in series. Percentage ratios of the various current components regarding the anode current at its current peaking are provided. The mechanisms involved in ESD discharge inside the diode-string clamp utilizing triple-well technologies are explained in detail, which has never been done anywhere in the literature based on simulations or measurements.\",\"PeriodicalId\":63422,\"journal\":{\"name\":\"电路与系统(英文)\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-05-31\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"电路与系统(英文)\",\"FirstCategoryId\":\"1093\",\"ListUrlMain\":\"https://doi.org/10.4236/cs.2018.95008\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"电路与系统(英文)","FirstCategoryId":"1093","ListUrlMain":"https://doi.org/10.4236/cs.2018.95008","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1

摘要

在这项工作中,基于二维器件和混合模式模拟,详细分析了利用三阱技术作为ESD保护VDD-VSS箝位器件的4二极管串的直流和瞬态特性。结果表明,在该器件中存在寄生pnp双极晶体管的作用,如果阳极偏压变高,则导致DC衬底泄漏的突然增加。通过对2000V PS模式HBM ESD放电事件的瞬态模拟,表明主要放电路径是由寄生pnpn晶闸管和寄生npn双极晶体管串联形成的放电路径。提供了各种电流分量相对于阳极电流在其电流峰值时的百分比比率。详细解释了利用三阱技术的二极管串箝位内ESD放电的机制,这在文献中从未基于模拟或测量进行过。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Discharge Characteristics of a Triple-Well Diode-String ESD Clamp
In this work, DC and transient characteristics of a 4 diode string utilizing triple-well technologies as a VDD-VSS clamp device for ESD protection are analyzed in detail based on 2-dimensional device and mixed-mode simulations. It is shown that there exists parasitic pnp bipolar transistor action in this device leading to a sudden increase in DC substrate leakage if anode bias is getting high. Through transient simulations for a 2000 V PS-mode HBM ESD discharge event, it is shown that the dominant discharge path is the one formed by a parasitic pnpn thyristor and a parasitic npn bipolar transistor in series. Percentage ratios of the various current components regarding the anode current at its current peaking are provided. The mechanisms involved in ESD discharge inside the diode-string clamp utilizing triple-well technologies are explained in detail, which has never been done anywhere in the literature based on simulations or measurements.
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