微纳电子与智能制造最新文献_第4页

Efficient Pre-stressed Harmonic Analysis of RF-Microresonators by Means of Model Order Reduction 基于模型降阶的射频微谐振器的有效预应力谐波分析

微纳电子与智能制造 Pub Date : 2006-04-24 DOI: 10.1109/ESIME.2006.1643943

L. Del Tin, R. Gaddi, A. Gnudi, E. Rudnyi, A. Greiner, J. Korvink

引用次数: 2

Design of High Performance Surface Transverse Waver Resonators 高性能表面横波谐振器的设计

微纳电子与智能制造 Pub Date : 2006-04-24 DOI: 10.1109/ESIME.2006.1643944

S.T. Wang, Mei-Hui Chung, Chunlei Yu

引用次数: 0

Modeling New Design of Fluidic Microvalves 流体微阀的建模新设计

微纳电子与智能制造 Pub Date : 2006-04-24 DOI: 10.1109/ESIME.2006.1643971

A. Pandolfi, M. Ortiz

引用次数: 4

Simulation of Impact Rupture in Polysilicon Mems 多晶硅Mems冲击破裂模拟

微纳电子与智能制造 Pub Date : 2006-04-24 DOI: 10.1109/ESIME.2006.1643984

A. Corigliano, F. Cacchione, A. Frangi, S. Zerbini

引用次数: 5

Combined Fracture, Delamination Risk and Fatigue Evaluation of Advanced Microelectronics Applications towards RSM/DOE Concepts 断裂、分层风险和疲劳综合评估在RSM/DOE概念中的先进微电子应用

微纳电子与智能制造 Pub Date : 2006-04-24 DOI: 10.1109/ESIME.2006.1644042

J. Auersperg, R. Dudek, B. Michel

{"title":"Combined Fracture, Delamination Risk and Fatigue Evaluation of Advanced Microelectronics Applications towards RSM/DOE Concepts","authors":"J. Auersperg, R. Dudek, B. Michel","doi":"10.1109/ESIME.2006.1644042","DOIUrl":"https://doi.org/10.1109/ESIME.2006.1644042","url":null,"abstract":"Microelectronic assemblies are basically compounds of several high precision materials with quite different Young's moduli and thermal expansion coefficients (CTE). Additionally, various kinds of inhomogeneity, residual stresses generated by several steps of the manufacturing process and extreme thermal environmental conditions contribute to interface delamination, chip cracking and fatigue of solder interconnects. For that reason, numerical investigations by means of nonlinear FEA together with conventional strength hypotheses are frequently used for design optimizations and sensitivity analyses. So, design studies on the basis of parameterized FE-models and DOE/RSM-approaches help to optimize electronic components at early phases of the product development process. But, this methodology typically bases on classical stress/strain strength evaluations or/and life time estimations of solder interconnects using modified Coffin-Manson approaches, whereas delamination or bulk fracture mechanisms usually remain unconsidered. By means of a representative microelectronics assembly this contribution is going to figure out and discuss ways and challenges of using numerical fatigue evaluation and fracture mechanics approaches in connection with parameterized finite element modeling based DOE/RSM-concepts. That is, the evaluation of mixed mode interface delamination phenomena utilizing the VCCT-methodology, classical strength hypotheses along with fracture mechanics approaches and modified Coffin-Manson thermal fatigue estimation of solder joints will be simultaneously applied within a multi-objective optimization towards a thermo-mechanical reliable design","PeriodicalId":60796,"journal":{"name":"微纳电子与智能制造","volume":"163 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2006-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83187966","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Drop Simulation and Stress Analysis of MEMS Devices MEMS器件跌落仿真及应力分析

微纳电子与智能制造 Pub Date : 2006-04-24 DOI: 10.1109/ESIME.2006.1643999

T. Hauck, G. Li, A. McNeill, H. Knoll, M. Ebert, J. Bagdahn

引用次数: 24

Simulation and analysis for typical package assembly manufacture 典型封装装配制造的仿真与分析

微纳电子与智能制造 Pub Date : 2006-04-24 DOI: 10.1109/ESIME.2006.1643949

Y. Liu, S. Irving, D. Desbiens, T. Luk

{"title":"Simulation and analysis for typical package assembly manufacture","authors":"Y. Liu, S. Irving, D. Desbiens, T. Luk","doi":"10.1109/ESIME.2006.1643949","DOIUrl":"https://doi.org/10.1109/ESIME.2006.1643949","url":null,"abstract":"The manufacturing process for package assembly is a key to assuring the reliability and quality of the semiconductor products. There are a significant number of challenging mechanics problems in assembly manufacturing process that may lead to the failure of die, delamination and package cracking. Identifying potential root causes of quality and reliability problems during the development of an assembly process and during package design is very important; it can reduce scrap during manufacturing, save development time, as well as help insure the product meets the requirements of customers. Simulation can find the root cause quickly and accurately, leading to reduced time and cost. It enables experiments that are too costly to be done by empirical methods. Using simulation we can find the conditions that optimize cost, performance and reliability under different sets of conditions. This paper focuses on modeling and simulation for typical package assembly manufacture processes which have large impact to the product quality and reliability. A finite element framework is developed to simulate the assembly package manufacturing process utilizing the ANSYS software platform. The framework tools are utilized to maximize the robustness of the assembly process in order to eliminate reliability issues, fast run time and minimize costs in development and from manufacturing scrap.","PeriodicalId":60796,"journal":{"name":"微纳电子与智能制造","volume":"33 1","pages":"1-10"},"PeriodicalIF":0.0,"publicationDate":"2006-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78765746","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 14

Design, Experiment and Analysis of the Solder on Rubber (SOR) structure of WLCSP WLCSP橡胶焊料(SOR)结构的设计、实验与分析

微纳电子与智能制造 Pub Date : 2006-04-24 DOI: 10.1109/ESIME.2006.1643969

C. Yuan, G.Q. Zhang, Ching-Shun Huang, Chun-Hui Yu, Chin-Cheng Yang, Wen-Kung Yang, M. Yew, Cheng-Nan Han, K. Chiang

引用次数: 0

Thermal Cycle Reliability of 3D Chip Stacked Package Using Pb-free Solder Bumps: Parameter Study by FEM Analysis 采用无铅凸点的三维芯片堆叠封装热循环可靠性:有限元分析参数研究

微纳电子与智能制造 Pub Date : 2006-04-24 DOI: 10.1109/ESIME.2006.1644002

C. Noritake, P. Limaye, M. Gonzalez, B. Vandevelde

{"title":"Thermal Cycle Reliability of 3D Chip Stacked Package Using Pb-free Solder Bumps: Parameter Study by FEM Analysis","authors":"C. Noritake, P. Limaye, M. Gonzalez, B. Vandevelde","doi":"10.1109/ESIME.2006.1644002","DOIUrl":"https://doi.org/10.1109/ESIME.2006.1644002","url":null,"abstract":"This study is aimed at analysing the reliability of a three-dimensional (3D) chip stacked package under cyclic thermal loading. The critical areas in the 3D chip stacked package are defined with finite element modeling (FEM) based simulations to correlate the thermal cycling experiments. The 3D chip stacked package consists of two 300mum thick Si chips vertically connected with Sn-Ag-Cu solder bump joints and then assembled on a conventional FR-4 printed circuit aboard (PCB). Two thermal cycle conditions are studied, namely: -40 to 125degC and 0 to 100degC. FEM simulations indicate that in both conditions, the critical failure location is expected to be in the chip side region of the corner solder bump of the lower chip connecting the package to the PCB. Creep strain per single thermal cycle averaged over a critical damage volume; Deltaepsivcr is used as the damage parameter. Furthermore, we have investigated the possible approaches to improve the thermo-mechanical reliability for this package. The results indicate that adding an underfill or thinning Si chips will achieve lower creep strain in solder bumps. Furthermore, the stress levels in Si and Cu via in the Si chip are low. Therefore fracture of Si chips and fatigue of Cu vias is not expected under thermal cycling conditions","PeriodicalId":60796,"journal":{"name":"微纳电子与智能制造","volume":"230 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2006-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91264713","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 18

Thermo-mechanical Design of Resilient Contact Systems for Wafer Level Packaging 晶圆级封装弹性接触系统的热机械设计

微纳电子与智能制造 Pub Date : 2006-04-24 DOI: 10.1109/ESIME.2006.1644012

R. Dudek, H. Walter, R. Doering, B. Michel, T. Meyer, J. Zapf, H. Hedler

{"title":"Thermo-mechanical Design of Resilient Contact Systems for Wafer Level Packaging","authors":"R. Dudek, H. Walter, R. Doering, B. Michel, T. Meyer, J. Zapf, H. Hedler","doi":"10.1109/ESIME.2006.1644012","DOIUrl":"https://doi.org/10.1109/ESIME.2006.1644012","url":null,"abstract":"Wafer level packaging (WLP) technologies are cost effective packaging solutions which are used increasingly. Second level reliability, i.e. mainly the thermo-mechanical reliability during thermal cycling, is a major concern of WLP. To avoid excessive solder straining, solder balls have been replaced by resilient interconnects, which can adopt the main part of the thermal mismatch deformation. One solution combining an increased reliability on module level with advantages in processing and the capability of full wafer level test and burn-in is ELASTecreg (ELASTec hArr Elastic-bump on Silicon Technology), particularly developed for memory products. The new failure risks are mainly related to fatigue of the metallic redistribution layer (RDL). Parametric studies using finite element analyses (FEA) were performed to avoid excessive straining of the metal lines. A balance of metal straining and solder straining had to be achieved. Comparisons were made for different soft bump layouts and RDL patterns. Optimal solutions figured out by FEA were also investigated experimentally by thermal cycle tests. However, the thermo-mechanical characteristics like stress-strain behaviour and fatigue resistance of the metallic films are the most important parameters for reliability predictions. In particular, the elastic-plastic properties of thin metallic Cu and Ni films are shown to depend on features like film thickness, grain size and orientation, resulting in a thin film strength exceeding the bulk strength of the same metal by several hundred percent","PeriodicalId":60796,"journal":{"name":"微纳电子与智能制造","volume":"107 1","pages":"1-7"},"PeriodicalIF":0.0,"publicationDate":"2006-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81391810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 15