IEEE Embedded Systems Letters最新文献_第5页

PttAcc: Pipeline-Based Taylor Expansion Fitting Arctangent Angle Hardware Accelerator Design for Descriptor Duty in ORB-SLAM System 基于管道Taylor展开拟合arctan角的ORB-SLAM系统广义任务硬件加速器设计

IF 1.7 4区计算机科学

IEEE Embedded Systems Letters Pub Date : 2024-10-03 DOI: 10.1109/LES.2024.3472731

Meng Liu;Fei Xiao;Ruijie Wang;Peiyuan Wan;Zhijie Chen;Dejian Li;Chongfei Shen

引用次数: 0

A Provably Secure Scheme to Prevent Master Key Recovery by Fault Attack on AES Hardware 防止AES硬件故障攻击恢复主密钥的可证明安全方案

IF 1.7 4区计算机科学

IEEE Embedded Systems Letters Pub Date : 2024-10-03 DOI: 10.1109/LES.2024.3472673

Sneha Swaroopa;Sivappriya Manivannan;Rajat Subhra Chakraborty;Indrajit Chakrabarti

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引用次数: 0

Navigating Time and Energy Tradeoffs in Reactive Heterogeneous Systems 反应异构系统中导航时间和能量权衡

IF 1.7 4区计算机科学

IEEE Embedded Systems Letters Pub Date : 2024-10-01 DOI: 10.1109/LES.2024.3469278

Shaokai Lin;Tassilo Tanneberger;Jiahong Bi;Guangyu Feng;Yimo Xu;Julian Robledo;Robert Khasanov;Jeronimo Castrillon

引用次数: 0

Layered Scheduling: Toward Better Real-Time Lingua Franca 分层调度：走向更好的实时通用语

IF 1.7 4区计算机科学

IEEE Embedded Systems Letters Pub Date : 2024-09-27 DOI: 10.1109/LES.2024.3467992

Francesco Paladino;Erling Jellum;Efsane Soyer;Edward A. Lee

引用次数: 0

Software-Defined Watchdog Timers for Cyber-Physical Systems 用于网络物理系统的软件定义看门狗定时器

IF 1.7 4区计算机科学

IEEE Embedded Systems Letters Pub Date : 2024-09-25 DOI: 10.1109/LES.2024.3467332

Benjamin Asch;Erling Jellum;Marten Lohstroh;Edward A. Lee

引用次数: 0

GNN-MiCS: Graph Neural-Network-Based Bounding Time in Embedded Mixed-Criticality Systems 嵌入式混合临界系统中基于图神经网络的边界时间

IF 1.7 4区计算机科学

IEEE Embedded Systems Letters Pub Date : 2024-09-23 DOI: 10.1109/LES.2024.3466268

Behnaz Ranjbar;Paul Justen;Akash Kumar

引用次数: 0

A Scalable Dynamic Segmented Bus Interconnect for Neuromorphic Architectures 面向神经形态体系结构的可扩展动态分段总线互连

IF 1.7 4区计算机科学

IEEE Embedded Systems Letters Pub Date : 2024-09-23 DOI: 10.1109/LES.2024.3452551

Phu Khanh Huynh;Ilknur Mustafazade;Francky Catthoor;Nagarajan Kandasamy;Anup Das

{"title":"A Scalable Dynamic Segmented Bus Interconnect for Neuromorphic Architectures","authors":"Phu Khanh Huynh;Ilknur Mustafazade;Francky Catthoor;Nagarajan Kandasamy;Anup Das","doi":"10.1109/LES.2024.3452551","DOIUrl":"https://doi.org/10.1109/LES.2024.3452551","url":null,"abstract":"Large-scale neuromorphic architectures consist of computing tiles that communicate spikes using a shared interconnect. We propose ADIONA, a dynamic segmented bus interconnect to address design scalability while reducing energy and latency of spike traffic. ADIONA consists of parallel bus lanes arranged in a ladder-shaped structure that allows any tile to connect to another, offers multiple routing options for communication links, and provides a high level of customization for different mapping scenarios and use cases. Each lane in the ladder bus is partitioned into segments using lightweight bufferless switches. Based on compile-time communication information, these switches can be dynamically reconfigured at runtime to execute the target application. Our dynamic segmented bus interconnect substantially enhances hardware utilization, improves fault tolerance, and offers adaptability to execute different applications on a single hardware platform. We evaluate ADIONA using three synthetic and three realistic machine learning workloads on a cycle-accurate neuromorphic simulator. Our results show that ADIONA reduces energy consumption by \u0000<inline-formula> <tex-math>$2.1times $ </tex-math></inline-formula>\u0000, latency by \u0000<inline-formula> <tex-math>$40times $ </tex-math></inline-formula>\u0000, and interconnect area by \u0000<inline-formula> <tex-math>$2times $ </tex-math></inline-formula>\u0000, compared to a state-of-the-art interconnect for neuromorphic systems.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 4","pages":"505-508"},"PeriodicalIF":1.7,"publicationDate":"2024-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142777790","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An Embedded Module of Enhanced Turbo Product Code Algorithm 一种增强Turbo产品编码算法的嵌入式模块

IF 1.7 4区计算机科学

IEEE Embedded Systems Letters Pub Date : 2024-09-20 DOI: 10.1109/LES.2024.3464517

Jianjun Luo;Yifan Shen;Boming Huang;Michael Etzkorn;Hongqiang Chen;Cong Yu

引用次数: 0

Toward Dynamism in Distributed Lingua Franca Programs 面向分布式通用语言程序的动态

IF 1.7 4区计算机科学

IEEE Embedded Systems Letters Pub Date : 2024-09-20 DOI: 10.1109/LES.2024.3465408

Chadlia Jerad;Edward A. Lee

引用次数: 0

Time-Sensitive Networking in Low Latency Cyber-Physical Systems 低延迟网络物理系统中的时间敏感型网络连接