IEEE Embedded Systems Letters最新文献_第5页

XOR-Free Approach for Implementation of Polar Encoder 无xor的极坐标编码器实现方法

IF 1.7 4区计算机科学

IEEE Embedded Systems Letters Pub Date : 2024-11-11 DOI: 10.1109/LES.2024.3495657

Navin Kumar;Deepak Kedia;Gaurav Purohit

{"title":"XOR-Free Approach for Implementation of Polar Encoder","authors":"Navin Kumar;Deepak Kedia;Gaurav Purohit","doi":"10.1109/LES.2024.3495657","DOIUrl":"https://doi.org/10.1109/LES.2024.3495657","url":null,"abstract":"This letter presents a new algorithmic approach to construct an XOR-Free architecture for a nonsystematic polar encoder (NSPE). Optimization of XOR units is the main concern while implementing NSPE, which consumes a significant amount of dynamic power. To generate polar sequences of code length N, the approach uses <inline-formula> <tex-math>$(N/2)-1$ </tex-math></inline-formula> binary patterns extracted from the <inline-formula> <tex-math>$(N/2)^{mathrm { th}}$ </tex-math></inline-formula> order generator matrix <inline-formula> <tex-math>$G_{N/2}$ </tex-math></inline-formula> instead of <inline-formula> <tex-math>$G_{N}$ </tex-math></inline-formula>. The algorithm reduces the logical operations by virtue of the recursive patterns, thereby improving hardware (HW) cost. The pattern logics are inferred with 2:1 multiplexers and inverters, making the implementation XOR-Free. An auto HDL code generation script is written targeting variable code lengths (<inline-formula> <tex-math>$2{^{{3}}} leq {N} leq 2{^{{10}}}$ </tex-math></inline-formula>) for direct comparison with similar approaches, viz. stage folded and punctured NSPE design. The results show that the proposed architecture improves area by 31%–83% and power consumption by 15%–57% for various N and code rates (<inline-formula> <tex-math>$R{=}1$ </tex-math></inline-formula>, 1/2) on Virtex-6 FPGA devices.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"17 3","pages":"184-187"},"PeriodicalIF":1.7,"publicationDate":"2024-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144272954","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Hechi: A Hybrid Approach for Efficient Memory Reclamation Techniques in Mobile Systems 河池：移动系统中高效内存回收技术的混合方法

IF 1.7 4区计算机科学

IEEE Embedded Systems Letters Pub Date : 2024-11-11 DOI: 10.1109/LES.2024.3494854

Wanju Doh;Seoyoung Ko;Michael Jaemin Kim;Jung Ho Ahn

{"title":"Hechi: A Hybrid Approach for Efficient Memory Reclamation Techniques in Mobile Systems","authors":"Wanju Doh;Seoyoung Ko;Michael Jaemin Kim;Jung Ho Ahn","doi":"10.1109/LES.2024.3494854","DOIUrl":"https://doi.org/10.1109/LES.2024.3494854","url":null,"abstract":"Application startup time, the time it takes for an application to become visible to the user from startup, is a crucial factor affecting user experience in mobile systems. The startup time of applications switching from the background (switching time) depends largely on the number of pages read from storage. When an application starts for the first time or reloads after being killed, it suffers from longer startup time (cold-launch time) as it begins from scratch. To mitigate this, minimizing application kills while retaining essential data in main memory can help, but it involves a tradeoff: reclaiming more file-backed pages (<monospace>file</monospace> pages) slows down switching due to the overhead of fetching them from storage, while reclaiming more anonymous pages (<monospace>anon</monospace> pages) that not associated with any file risks app termination due to limited swap space. Hechi addresses this tradeoff using a hybrid memory reclamation approach. By deprioritizing the reclamation of essential file pages and dynamically adjusting the reclamation ratio of the two types of pages based on the system states, Hechi improves startup time by up to 17%.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"17 3","pages":"192-195"},"PeriodicalIF":1.7,"publicationDate":"2024-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144272851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Development of a Miniaturized Testing System for Resonant Frequency Difference Detection for Delay Line Surface Acoustic Wave Devices 延迟线表面声波器件谐振频差检测小型化测试系统的研制

IF 1.7 4区计算机科学

IEEE Embedded Systems Letters Pub Date : 2024-11-06 DOI: 10.1109/LES.2024.3486992

Tao Li;Rui Sun;Rong Zhang;Cuiping Li;Huimin Liu

引用次数: 0

Configurable Multiport Memory Architecture for High-Speed Data Communication 高速数据通信的可配置多端口存储器体系结构

IF 1.7 4区计算机科学

IEEE Embedded Systems Letters Pub Date : 2024-11-06 DOI: 10.1109/LES.2024.3485509

Narendra Singh Dhakad;Santosh Kumar Vishvakarma

引用次数: 0

Adaptive Extended Kalman Filtering for Battery State of Charge Estimation on STM32 基于STM32的电池状态估计自适应扩展卡尔曼滤波

IF 1.7 4区计算机科学

IEEE Embedded Systems Letters Pub Date : 2024-10-31 DOI: 10.1109/LES.2024.3489352

António Barros;Edoardo Peretti;Davide Fabroni;Diego Carrera;Pasqualina Fragneto;Giacomo Boracchi

引用次数: 0

Energy-Efficient Decoding and Encoding Hardware for Optimized Posit Arithmetic 优化正数算法的节能解码和编码硬件

IF 1.7 4区计算机科学

IEEE Embedded Systems Letters Pub Date : 2024-10-30 DOI: 10.1109/LES.2024.3485002

Aditya Anirudh Jonnalagadda;Rishi Thotli;Sreehari Veeramachaneni;Uppugunduru Anil Kumar;Syed Ershad Ahmed

{"title":"Energy-Efficient Decoding and Encoding Hardware for Optimized Posit Arithmetic","authors":"Aditya Anirudh Jonnalagadda;Rishi Thotli;Sreehari Veeramachaneni;Uppugunduru Anil Kumar;Syed Ershad Ahmed","doi":"10.1109/LES.2024.3485002","DOIUrl":"https://doi.org/10.1109/LES.2024.3485002","url":null,"abstract":"The posit number system represents a binary numerical format devised primarily to mitigate the shortcomings of the IEEE 754 floating-point standard commonly used in modern computer arithmetic. Unlike IEEE 754, which utilizes a fixed-width representation, posits offer a variable-size encoding, dynamically adjusting the number of bits allocated based on the magnitude of the represented number. This adaptability enables posits to provide enhanced precision across a broader range of values, addressing issues like gradual underflow and the multiple representations of zero and NaN values inherent in IEEE 754. However, the dynamic bit allocation also poses significant challenges in decoding the posit number into its constituent fields and packing back the fields of the resultant posit once the arithmetic operations have been performed. For posits to become a viable alternative to floating-points in practical computing systems, the decoding and encoding overheads of posits need to be minimized. Hence, the aim of this letter is to develop energy-efficient hardware for posit decoding and encoding. The proposed <inline-formula> <tex-math>$langle 16,2rangle $ </tex-math></inline-formula> posit decoders, Decoders A and B show an improvement of over 65% and 33% compared to literature in terms of energy requirements. Similarly, the proposed <inline-formula> <tex-math>$langle 16,2rangle $ </tex-math></inline-formula> encoder circuit is over 52% more energy-efficient than existing encoder circuits.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"17 3","pages":"131-134"},"PeriodicalIF":1.7,"publicationDate":"2024-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144272852","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Developing Compact Models Using Regression Confidence Forge Knowledge Distillation for IMU-Based Indoor Positioning System 基于回归置信度锻造知识精馏的室内定位系统紧凑模型研究

IF 1.7 4区计算机科学

IEEE Embedded Systems Letters Pub Date : 2024-10-28 DOI: 10.1109/LES.2024.3487236

Nur Achmad Sulistyo Putro;Jenq-Shiou Leu;Nias Ananto;Cries Avian;Muhammad Izzuddin Mahali;Setya Widyawan Prakosa

引用次数: 0

VANet: A Solution for Ventricular Arrhythmias Detection of IEGM on Embedded Devices 基于嵌入式设备的IEGM室性心律失常检测解决方案

IF 1.7 4区计算机科学

IEEE Embedded Systems Letters Pub Date : 2024-10-28 DOI: 10.1109/LES.2024.3483895

Chaoyao Shen;Cheng Chen;Meng Zhang

引用次数: 0

Design of an Embedded System for Integrated Underwater Communication and Detection 一种集成水下通信与探测的嵌入式系统设计

IF 1.7 4区计算机科学

IEEE Embedded Systems Letters Pub Date : 2024-10-24 DOI: 10.1109/LES.2024.3485608

Jing Yan;Lifang Cui;Xian Yang;Cailian Chen;Xinping Guan

引用次数: 0

DynHD: Hyperdimensional Computing Approach for Efficient Radar Spectrum Classification 高效雷达频谱分类的超维计算方法

IF 1.7 4区计算机科学

IEEE Embedded Systems Letters Pub Date : 2024-10-24 DOI: 10.1109/LES.2024.3485638

Zhuowen Zou;Yang Ni;SungHeon Jeong;Satish Ravindran;Binbin Shi;Phil Chen;Mohsen Imani

{"title":"DynHD: Hyperdimensional Computing Approach for Efficient Radar Spectrum Classification","authors":"Zhuowen Zou;Yang Ni;SungHeon Jeong;Satish Ravindran;Binbin Shi;Phil Chen;Mohsen Imani","doi":"10.1109/LES.2024.3485638","DOIUrl":"https://doi.org/10.1109/LES.2024.3485638","url":null,"abstract":"Radar technology plays a critical role in target detection, classification, and tracking. However, the computational demands of training deep neural networks (DNNs) on radar signals can be overwhelming, posing challenges for edge devices with limited energy and computing resources. In this article, we propose leveraging hyperdimensional computing (HDC), a brain-inspired computing paradigm, as an efficient alternative. HDC utilizes high-dimensional vectors for information representation and processing, offering robustness and energy efficiency. We propose a novel HDC classification algorithm named DynHD, with a dynamic HDC encoder that adapts to more challenging radar spectrum recognition tasks. We designed this mechanism to provide great flexibility to the HDC encoder that is otherwise fixed. Our evaluations demonstrate that HDC-based approaches achieve comparable accuracy to DNN-based methods with lower-computational complexity, making them suitable for resource-constrained devices. We achieve significant improvements in latency during training and inference phases, enabling efficient processing of radar signals on edge devices.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"17 2","pages":"95-98"},"PeriodicalIF":1.7,"publicationDate":"2024-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10734137","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143845510","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0