IEEE Embedded Systems Letters最新文献

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Digital Circuit Design for the Square Root Computation by Means of Unfolding Techniques 利用展开技术进行平方根计算的数字电路设计
IF 1.7 4区 计算机科学
IEEE Embedded Systems Letters Pub Date : 2024-07-29 DOI: 10.1109/LES.2024.3435477
Ricardo Paez Villa;Jorge Rivera;Juan José Raygoza;Edwin Becerra;Susana Ortega
{"title":"Digital Circuit Design for the Square Root Computation by Means of Unfolding Techniques","authors":"Ricardo Paez Villa;Jorge Rivera;Juan José Raygoza;Edwin Becerra;Susana Ortega","doi":"10.1109/LES.2024.3435477","DOIUrl":"10.1109/LES.2024.3435477","url":null,"abstract":"Two fixed-point (FP) square root designs based on a bit-by-bit nonrestoring algorithm are unfolded, and compared to an FP pipelined design based on the same algorithm. One of them is unfolded from a bit-serial design, while the other design is unfolded from a smaller version of the pipelined design that has a digit size of 2, for this reason, it is cataloged as “unfolding based.” Hardware utilization is estimated with the theoretical use in the RTL designs and the synthesis report as an auxiliary tool. Results show that the unfolding-based design is comparable and even surpasses the pipelined design when it comes to outputting a first result, being 19.47% faster and using 32.59% of memory of the pipelined design.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"17 1","pages":"62-65"},"PeriodicalIF":1.7,"publicationDate":"2024-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141871134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
On the Retiming for Register Minimization by Means of Breadth Coefficients Matrix 论通过广度系数矩阵实现寄存器最小化的重定时
IF 1.7 4区 计算机科学
IEEE Embedded Systems Letters Pub Date : 2024-07-29 DOI: 10.1109/LES.2024.3435388
H. Emmanuel Muñoz;Jorge Rivera;Susana Ortega-Cisneros;Diego H. Gaytán-Rivas
{"title":"On the Retiming for Register Minimization by Means of Breadth Coefficients Matrix","authors":"H. Emmanuel Muñoz;Jorge Rivera;Susana Ortega-Cisneros;Diego H. Gaytán-Rivas","doi":"10.1109/LES.2024.3435388","DOIUrl":"10.1109/LES.2024.3435388","url":null,"abstract":"This letter is focused in the retiming technique for register minimization. This technique was presented as a minimum-cost linear problem, where the use of a fanout gadget was proposed to the model nodes (the functional blocks) in a digital circuit with multiple output edges to obtain a retiming solution <inline-formula> <tex-math>$r(V)$ </tex-math></inline-formula> with integer values. The goal of this technique is to minimize the function <inline-formula> <tex-math>${mathrm { COST}}^{prime } =sum _{e} beta (e)omega _{r} (e)$ </tex-math></inline-formula> subject to feasibility and clock period constraints. The determination of the breadth coefficients <inline-formula> <tex-math>$beta (e)$ </tex-math></inline-formula> could be cumbersome for large digital circuits, as there is no suitable method in the literature. Based on some concepts from graph theory and linear algebra, an algorithm for computing the breadth coefficients is proposed. An example is presented in order to illustrate the performance of the proposed algorithm as calculations for the breadth coefficients are effortless determined.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"17 1","pages":"58-61"},"PeriodicalIF":1.7,"publicationDate":"2024-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141871021","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Hardware-Aware Bayesian Neural Architecture Search of Quantized CNNs 量化 CNN 的硬件感知贝叶斯神经架构搜索
IF 1.7 4区 计算机科学
IEEE Embedded Systems Letters Pub Date : 2024-07-26 DOI: 10.1109/LES.2024.3434379
Mathieu Perrin;William Guicquero;Bruno Paille;Gilles Sicard
{"title":"Hardware-Aware Bayesian Neural Architecture Search of Quantized CNNs","authors":"Mathieu Perrin;William Guicquero;Bruno Paille;Gilles Sicard","doi":"10.1109/LES.2024.3434379","DOIUrl":"10.1109/LES.2024.3434379","url":null,"abstract":"Advances in neural architecture search (NAS) now provide a crucial assistance to design hardware-efficient neural networks (NNs). This letter presents NAS for resource-efficient, weight-quantized convolutional NNs (CNNs), under computational complexity constraints (model size and number of computations). Bayesian optimization is used to efficiently search for traceable CNN architectures within a continuous embedding space. This embedding is the latent space of a neural architecture autoencoder, regularized with a maximum mean discrepancy penalization and a convex latent predictor of parameters. On CIFAR-100, and without quantization, we obtain 75% test accuracy with less than 2.5M parameters and 600M operations. NAS experiments on STL-10 with 32, 8, and 4 bit weights outperform some high-end architectures while enabling drastic model size reduction (6 Mb–840 kb). It demonstrates our method’s ability to discover lightweight and high-performing models, while showcasing the importance of quantization to improve the tradeoff between accuracy and model size.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"17 1","pages":"42-45"},"PeriodicalIF":1.7,"publicationDate":"2024-07-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141782194","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An Endogenous Security Study of Telematics Box in Intelligent Connected Vehicles 智能网联汽车车载信息箱的内生安全研究
IF 1.7 4区 计算机科学
IEEE Embedded Systems Letters Pub Date : 2024-07-23 DOI: 10.1109/LES.2024.3432593
Zhen Zhang;Yuezhong Zhang;Jinfeng Zhang;Jichao Xie;Shaoxun Liu
{"title":"An Endogenous Security Study of Telematics Box in Intelligent Connected Vehicles","authors":"Zhen Zhang;Yuezhong Zhang;Jinfeng Zhang;Jichao Xie;Shaoxun Liu","doi":"10.1109/LES.2024.3432593","DOIUrl":"10.1109/LES.2024.3432593","url":null,"abstract":"Intelligent connected vehicles (ICVs) are the result of technological advancements in the new era, greatly enhancing the driving experience. However, due to the complex nature of the system, the intelligence of devices, and the connectivity of data, a complex physical fusion system has been created. The in-vehicle Telematics Box (T-Box), serving as the central communication and data hub, faces challenges, such as network vulnerabilities, data privacy, and malicious attacks through untrusted software updates. Therefore, an in-vehicle T-Box with high reliability, security, and performance is an urgent product in the era of the Internet of Vehicles. This article investigates the endogenous security of the T-Box in ICV, with a focus on the integration of dynamic heterogeneous redundancy (DHR) architecture. The underlying idea is to transform the original system into multiple heterogeneous systems, where some of them handle the same business functions. By applying a consensus mechanism to detect malicious nodes and dynamically scheduling healthy nodes into the working mode, a self-purifying defense system with intrinsic security is formed. This design approach endows the T-Box with inherent defense capabilities against unknown vulnerabilities. Meanwhile, the in-vehicle T-Box is redesigned in the software and hardware implementation scheme. Experimental results demonstrate that the new design notably enhances and ensures the robust stability and elevated reliability of the in-vehicle T-Box. Evidently, the upgraded T-Box ensures the safe processing of in-vehicle CAN bus data.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 4","pages":"501-504"},"PeriodicalIF":1.7,"publicationDate":"2024-07-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141782193","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Analysis of Outdoor Air Quality Using Low-Cost MEMS-Based Electronic Nose and Gas Analyzer With Multivariate Statistical Approach 利用低成本 MEMS 电子鼻和气体分析仪分析室外空气质量
IF 1.7 4区 计算机科学
IEEE Embedded Systems Letters Pub Date : 2024-07-18 DOI: 10.1109/LES.2024.3431214
Tushar Gawande;Raghavendra Deshmukh;Sharvari Deshmukh
{"title":"Analysis of Outdoor Air Quality Using Low-Cost MEMS-Based Electronic Nose and Gas Analyzer With Multivariate Statistical Approach","authors":"Tushar Gawande;Raghavendra Deshmukh;Sharvari Deshmukh","doi":"10.1109/LES.2024.3431214","DOIUrl":"10.1109/LES.2024.3431214","url":null,"abstract":"In this letter, MEMS gas sensors-based electronic nose (e-nose) was developed and used for odorant evaluations at different parts of the city. A gas analyzer, in conjunction with sensorial analysis, was performed for different odorous samples. The design of experiments that consisted of eight experimental sets was developed to the selectivity and sensitivity of the developed sensor array following the actual environmental scenario. Advanced multivariate statistical approaches, such as linear discriminant analyses and K-means, were used to describe sample similarity and discrimination ability of the system. The e-nose data processing exhibits satisfactory discrimination between air samples with more than 97% variability. A validated partial least-square (PLS) model foresees good co-relation between e-nose measurement and gas analyzer analysis. Analysis of variance shows that the model is a good fit with significantly reduced RMSE values and high <inline-formula> <tex-math>$R^{2}$ </tex-math></inline-formula> values. The finding indicates that an e-nose unit could be a low-cost solution for environmental measurement-based odorant emissions measurement.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"17 1","pages":"18-21"},"PeriodicalIF":1.7,"publicationDate":"2024-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141743272","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Co-Optimization of Software and Hardware for PCIe-Based Small Packet DMA Transfer 基于 PCIe 的小数据包 DMA 传输的软硬件协同优化
IF 1.7 4区 计算机科学
IEEE Embedded Systems Letters Pub Date : 2024-07-17 DOI: 10.1109/LES.2024.3429544
Xiaotian Gu;Lisong Shao;Ningfeng Bai;Guosheng Zhang;Xinyi Zhang
{"title":"A Co-Optimization of Software and Hardware for PCIe-Based Small Packet DMA Transfer","authors":"Xiaotian Gu;Lisong Shao;Ningfeng Bai;Guosheng Zhang;Xinyi Zhang","doi":"10.1109/LES.2024.3429544","DOIUrl":"10.1109/LES.2024.3429544","url":null,"abstract":"To meet the development needs of high-performance networks, the efficiency of PCIe DMA with small packet transmissions emerges as a critical performance bottleneck. For the purpose improving DMA transfer for small packets over PCIe, we focus on the symbiotic co-optimization of software and hardware. By enhancing the software driver with descriptor prefetching, harnessing the outstanding capability at the hardware level, and using multicore for parallel processing, the system’s bandwidth has been significantly improved, particularly for the small packets transfers. Postoptimization, we test the DMA read and write bandwidth and utilization rate performance on VC709 FPGA. In a randomized test scenario, the average DMA read bandwidth is approximately 5.3 GB/s, representing a 123% improvement compared to the unoptimized system bandwidth. The average DMA write bandwidth is approximately 5.8 GB/s, representing a 136% improvement compared to the unoptimized system bandwidth. Additionally, in the randomized test scenario, the average read and write latencies improved by 15.12% and 23.96%, respectively.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"17 1","pages":"6-9"},"PeriodicalIF":1.7,"publicationDate":"2024-07-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141743273","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Securing Binarized Neural Networks via PUF-Based Key Management in Memristive Crossbar Arrays 通过 Memristive Crossbar 阵列中基于 PUF 的密钥管理确保二值化神经网络的安全
IF 1.7 4区 计算机科学
IEEE Embedded Systems Letters Pub Date : 2024-07-02 DOI: 10.1109/LES.2024.3422294
Gokulnath Rajendran;Debajit Basak;Suman Deb;Anupam Chattopadhyay
{"title":"Securing Binarized Neural Networks via PUF-Based Key Management in Memristive Crossbar Arrays","authors":"Gokulnath Rajendran;Debajit Basak;Suman Deb;Anupam Chattopadhyay","doi":"10.1109/LES.2024.3422294","DOIUrl":"10.1109/LES.2024.3422294","url":null,"abstract":"Binarized neural networks (BNNs) are a subset of deep neural networks proposed to consume less computational resources with a smaller energy budget. Recent studies showed that memristor-based in-memory computing architectures can be constructed to accelerate BNNs, with better performance compared to traditional CMOS technologies. The memristor nonvolatility utilized for in-memory computing poses a notable threat to theft attacks in the presence of adversaries with physical access. This motivates us to introduce two novel protection methodologies to safeguard the model parameters of BNNs in the memristive crossbar. We propose to take advantage of physical unclonable functions (PUFs), which can be implemented using memristor-based crossbars for protecting BNN. This feature provides superior security compared to the traditional stored-key-based schemes. We provide circuit-level hardware designs to implement our methodologies with negligible additional overhead compared to an unprotected design and detailed supporting analysis to validate our security claims.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"17 1","pages":"30-33"},"PeriodicalIF":1.7,"publicationDate":"2024-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141508763","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Dependable and Low-Cost CCSDS 123 Hyperspectral Image Compressor 可靠、低成本的 CCSDS 123 高光谱图像压缩器
IF 1.7 4区 计算机科学
IEEE Embedded Systems Letters Pub Date : 2024-07-01 DOI: 10.1109/LES.2024.3420934
Wesley Grignani;Douglas A. Santos;Felipe Viel;Luigi Dilillo;Douglas R. Melo
{"title":"A Dependable and Low-Cost CCSDS 123 Hyperspectral Image Compressor","authors":"Wesley Grignani;Douglas A. Santos;Felipe Viel;Luigi Dilillo;Douglas R. Melo","doi":"10.1109/LES.2024.3420934","DOIUrl":"10.1109/LES.2024.3420934","url":null,"abstract":"One of the most critical challenges in applications that use hyperspectral image (HSI) is the demand for compression, which affects restrictions on the storage capacity and processing in space applications. In addition, these systems that operate in space are susceptible to faults due to adverse conditions and require the implementation of protection techniques to mitigate these faults and ensure correct operation. This letter aimed to implement a fault-tolerant CCSDS 123 HSI compressor using a hardware description language (HDL) and fault-tolerant techniques like triple modular redundancy (TMR) and Hamming error correcting code (ECC). A fault injection campaign verified the reliability of the techniques. Results show that the implementation accelerated the application by <inline-formula> <tex-math>$24times $ </tex-math></inline-formula> compared to the software solution. The standard solution can process 20.57 MSa/s, and the hardened solution can process 13.81 MSa/s using <inline-formula> <tex-math>$2.2times $ </tex-math></inline-formula> more look-up tables (LUTs) and <inline-formula> <tex-math>$1.4times $ </tex-math></inline-formula> more flip-flops (FFs). The low cost observed in the results makes this implementation a suitable solution for application in space systems targeting resource-efficient devices.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"17 1","pages":"54-57"},"PeriodicalIF":1.7,"publicationDate":"2024-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141508764","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Boosting AES Intrinsic Resilience Using Split SubBytes Round Function Against Power Attacks 利用分拆子字节轮函数提升 AES 固有弹性,抵御功率攻击
IF 1.7 4区 计算机科学
IEEE Embedded Systems Letters Pub Date : 2024-06-27 DOI: 10.1109/LES.2024.3420226
Vishnu Padmakumar;Titu Mary Ignatius;Thockchom Birjit Singha;Roy Paily Palathinkal;Shaik Rafi Ahamed
{"title":"Boosting AES Intrinsic Resilience Using Split SubBytes Round Function Against Power Attacks","authors":"Vishnu Padmakumar;Titu Mary Ignatius;Thockchom Birjit Singha;Roy Paily Palathinkal;Shaik Rafi Ahamed","doi":"10.1109/LES.2024.3420226","DOIUrl":"10.1109/LES.2024.3420226","url":null,"abstract":"Advanced encryption standard’s (AES) vulnerabilities surfaced with power-side channel attacks (PSCAs). Enhancing security by adding extra countermeasure circuitry introduces significant hardware overheads, which are impractical for resource-constrained Internet of Things (IoT) edge devices. This letter proposes an alternative approach, focusing on the AES design itself to enable lightweight countermeasures. Targeting the SubBytes round operation as the vulnerable point, the operation is split across different clock cycles to minimize side-channel information leakage. We investigated 12-clock, 22-clock, 42-clock, 82-clock, and 162-clock AES designs, among which the 82-clock version stands out as the optimal choice, providing efficient hardware resource utilization. Evaluation using hardware security metrics, such as measurements to disclose (MTD) and signal to noise ratio (SNR), confirms its superior security and reduced information leakage compared to other designs. Power traces for attacks are generated on both application-specific integrated circuit (ASIC) and field-programmable gate array (FPGA) platforms, maintaining a consistent 16 MHz design frequency with traces sampled at 1 GSa/s.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"17 1","pages":"10-13"},"PeriodicalIF":1.7,"publicationDate":"2024-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141508765","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Software Implementation of Fast List Decoder for PAC Codes PAC 码快速列表解码器的软件实现
IF 1.7 4区 计算机科学
IEEE Embedded Systems Letters Pub Date : 2024-06-20 DOI: 10.1109/LES.2024.3417413
Hang Yin;Jingxin Dai;Yansong Lv;Yuhuan Wang;Rui Lv
{"title":"Software Implementation of Fast List Decoder for PAC Codes","authors":"Hang Yin;Jingxin Dai;Yansong Lv;Yuhuan Wang;Rui Lv","doi":"10.1109/LES.2024.3417413","DOIUrl":"10.1109/LES.2024.3417413","url":null,"abstract":"In this letter, a novel high throughput software polarization-adjusted convolutional (PAC) decoder based on the four-node fast list (FFL) decoding algorithm is proposed. To improve the parallel processing capabilities of the proposed decoder, we effectively parallel map the FFL decoding algorithm to processors by using the single-instruction-multiple-data (SIMD) instruction set to decode multiple frames of data in parallel. Moreover, the proposed decoder has sufficient generality to be implemented on X86 and ARM processors (NEON, SSE, and AVX256 instruction sets). Experimentations show that the proposed software PAC decoder can achieve 26.256 Mb/s.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"17 1","pages":"14-17"},"PeriodicalIF":1.7,"publicationDate":"2024-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141508766","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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