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FedTinyWolf—A Memory Efficient Federated Embedded Learning Mechanism FedTinyWolf - 一种内存高效的联合嵌入式学习机制
IF 1.7 4区 计算机科学
IEEE Embedded Systems Letters Pub Date : 2024-09-17 DOI: 10.1109/LES.2024.3462638
Subhrangshu Adhikary;Subhayu Dutta
{"title":"FedTinyWolf—A Memory Efficient Federated Embedded Learning Mechanism","authors":"Subhrangshu Adhikary;Subhayu Dutta","doi":"10.1109/LES.2024.3462638","DOIUrl":"10.1109/LES.2024.3462638","url":null,"abstract":"Embedded intelligence is a challenging field in engineering given its resource-constrained environment which regular machine learning algorithms demand. Most embedded intelligence models are trained on a computer and then the learned parameters are transferred to the embedded devices to enable decision making. Although training the model within a microcontroller is possible, the state-of-the-art method requires further optimization. Moreover, federated learning (FL) is used in the state of the art to protect data privacy while training a deep learning model at edge level. Embedded learning models require memory enhancements to improve on-device FL. In this experiment, we have performed memory enhancement of gray wolf optimizer after finding it suitable for the purpose and implemented it to create edge-level, resource-efficient, data privacy preserving on-device federated training of embedded intelligence models. The performances are benchmarked on 13 open-sourced datasets showing a mean 10.8% accuracy enhancement.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 4","pages":"513-516"},"PeriodicalIF":1.7,"publicationDate":"2024-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142263901","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
SCALLER: Standard Cell Assembled and Local Layout Effect-Based Ring Oscillators SCALLER：基于标准单元组装和局部布局效应的环形振荡器
IF 1.7 4区 计算机科学
IEEE Embedded Systems Letters Pub Date : 2024-09-12 DOI: 10.1109/LES.2024.3459730
Muayad J. Aljafar;Zain Ul Abideen;Adriaan Peetermans;Benedikt Gierlichs;Samuel Pagliarini
{"title":"SCALLER: Standard Cell Assembled and Local Layout Effect-Based Ring Oscillators","authors":"Muayad J. Aljafar;Zain Ul Abideen;Adriaan Peetermans;Benedikt Gierlichs;Samuel Pagliarini","doi":"10.1109/LES.2024.3459730","DOIUrl":"10.1109/LES.2024.3459730","url":null,"abstract":"This letter presents a technique that enables very fine tunability of the frequency of ring oscillators (ROs). Multiple ROs with different numbers of tunable elements were designed and fabricated in a 65-nm CMOS technology. A tunable element consists of two inverters under different local layout effects (LLEs) and a multiplexer. LLEs impact the transient response of inverters deterministically and allow to establish a fine tunable mechanism even in the presence of large process variation. The entire RO is digital and its layout is standard-cell compatible. We demonstrate the tunability of multistage ROs with post-silicon measurements of oscillation frequencies in the range of 80–900 MHz and tuning steps of 90 kHz.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 4","pages":"493-496"},"PeriodicalIF":1.7,"publicationDate":"2024-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142199415","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Comparing XML and JSON Characteristics as Formats for Data Serialization Within Ultralow Power Embedded Systems 比较 XML 和 JSON 作为超低功耗嵌入式系统数据序列化格式的特点
IF 1.7 4区 计算机科学
IEEE Embedded Systems Letters Pub Date : 2024-08-28 DOI: 10.1109/LES.2024.3450576
James Gerrans;R. Simon Sherratt
{"title":"Comparing XML and JSON Characteristics as Formats for Data Serialization Within Ultralow Power Embedded Systems","authors":"James Gerrans;R. Simon Sherratt","doi":"10.1109/LES.2024.3450576","DOIUrl":"10.1109/LES.2024.3450576","url":null,"abstract":"Javascript object notation (JSON) and extensible markup language (XML) are two data serialization methods that have been compared over many applications, including client-server transmission, Internet communication, and large-scale data storage. Due to the smaller file size, JSON is faster for transmitting data. However, XML is better for sending complex data structures. This letter compares the two data formats in the context of an embedded system, considering factors, such as time, memory, and power to identify efficient characteristics of each method. Programs for each format were written, optimized, and compared for the same dataset. The JSON file was found to be 24.7% smaller than the XML file. This led to a shorter program run-time and less power being consumed when reading and processing the file. However, the program to deserialize the XML file took up 16.7% less flash memory than its JSON counterpart. Overall, JSON was found to be a better choice for systems when collecting large amounts of data, requiring high speed communication, or running for an extended period between battery charges. However, XML is proposed for systems that have limited flash memory.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 4","pages":"489-492"},"PeriodicalIF":1.7,"publicationDate":"2024-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142199416","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
IEEE Embedded Systems Letters Publication Information IEEE Embedded Systems Letters 出版信息
IF 1.7 4区 计算机科学
IEEE Embedded Systems Letters Pub Date : 2024-08-28 DOI: 10.1109/LES.2024.3396921
{"title":"IEEE Embedded Systems Letters Publication Information","authors":"","doi":"10.1109/LES.2024.3396921","DOIUrl":"https://doi.org/10.1109/LES.2024.3396921","url":null,"abstract":"","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 3","pages":"C2-C2"},"PeriodicalIF":1.7,"publicationDate":"2024-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10654459","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142090865","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Multidimensional Hardware Trojan Design Platform to Enhance Hardware Security 提高硬件安全性的多维硬件木马设计平台
IF 1.7 4区 计算机科学
IEEE Embedded Systems Letters Pub Date : 2024-08-01 DOI: 10.1109/LES.2024.3436701
Nilanjana Das;Mattis Hasler;Friedrich Pauls;Sebastian Haas
{"title":"A Multidimensional Hardware Trojan Design Platform to Enhance Hardware Security","authors":"Nilanjana Das;Mattis Hasler;Friedrich Pauls;Sebastian Haas","doi":"10.1109/LES.2024.3436701","DOIUrl":"10.1109/LES.2024.3436701","url":null,"abstract":"This letter proposes a novel kind of HT design named multidimensional HTs (MDHTs) and develops a method to generate configurable MDHT benchmark platform. The proposed MDHT circuits include multiple net(s) as trigger signals from each of the rarely activated, highly activated, and partially activated categories to increase MDHT’s adverse effects. The generated MDHT-infected circuits are tested by an unsupervised machine learning-based HT detection technique-controllability and observability for HT detection (COTD). Experimentation on ISCAS benchmarks ensures that the detection method is unable to detect the developed MDHT circuits as the nets belong to higher and partial activities are creating at least 50% and at most 80% false negative rate which validates the MDHT insertion framework in addition to the available HT benchmarks.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"17 1","pages":"46-49"},"PeriodicalIF":1.7,"publicationDate":"2024-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141882816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Acceleration of an Optimized Kvazaar All Intra Prediction on Embedded Systems Based on the Directional Texture Complexity 基于方向纹理复杂性的嵌入式系统上优化的 Kvazaar 全内预测加速度
IF 1.7 4区 计算机科学
IEEE Embedded Systems Letters Pub Date : 2024-08-01 DOI: 10.1109/LES.2024.3436511
James R. Majok;Mohammed Abo-Zahhad;Koji Inoue;Mohammed S. Sayed
{"title":"Acceleration of an Optimized Kvazaar All Intra Prediction on Embedded Systems Based on the Directional Texture Complexity","authors":"James R. Majok;Mohammed Abo-Zahhad;Koji Inoue;Mohammed S. Sayed","doi":"10.1109/LES.2024.3436511","DOIUrl":"10.1109/LES.2024.3436511","url":null,"abstract":"The high growth of real-time video applications on embedded systems poses challenges for practical encoders aiming to deliver high quality and high speed simultaneously. In real-world video applications, the slower preset in Kvazaar HEVC encoder can achieve impressive quality, with a penalty of extensive computational time. This is ultimately due to rate-distortion optimization that involves a comprehensive analysis of all possible quad-tree partitioning within the coding tree unit (CTU) structure, resulting in unpleasant encoding complexity. This letter proposes a method of accelerating All Intraprediction on Nvidia Jetson TX1 using early termination of CTU partitioning and a method of selecting only eight modes for intraframe search. The proposed technique reduces the running time of an optimized Kvazaar all intraprediction by 48.4% and 40.24% at slower and higher presets, respectively, with an average BD rate lost of 1.5% and 0.682% compared to the optimized Kvazaar running under the same coding configuration.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"17 1","pages":"38-41"},"PeriodicalIF":1.7,"publicationDate":"2024-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141882817","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Digital Circuit Design for the Square Root Computation by Means of Unfolding Techniques 利用展开技术进行平方根计算的数字电路设计
IF 1.7 4区 计算机科学
IEEE Embedded Systems Letters Pub Date : 2024-07-29 DOI: 10.1109/LES.2024.3435477
Ricardo Paez Villa;Jorge Rivera;Juan José Raygoza;Edwin Becerra;Susana Ortega
{"title":"Digital Circuit Design for the Square Root Computation by Means of Unfolding Techniques","authors":"Ricardo Paez Villa;Jorge Rivera;Juan José Raygoza;Edwin Becerra;Susana Ortega","doi":"10.1109/LES.2024.3435477","DOIUrl":"10.1109/LES.2024.3435477","url":null,"abstract":"Two fixed-point (FP) square root designs based on a bit-by-bit nonrestoring algorithm are unfolded, and compared to an FP pipelined design based on the same algorithm. One of them is unfolded from a bit-serial design, while the other design is unfolded from a smaller version of the pipelined design that has a digit size of 2, for this reason, it is cataloged as “unfolding based.” Hardware utilization is estimated with the theoretical use in the RTL designs and the synthesis report as an auxiliary tool. Results show that the unfolding-based design is comparable and even surpasses the pipelined design when it comes to outputting a first result, being 19.47% faster and using 32.59% of memory of the pipelined design.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"17 1","pages":"62-65"},"PeriodicalIF":1.7,"publicationDate":"2024-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141871134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
On the Retiming for Register Minimization by Means of Breadth Coefficients Matrix 论通过广度系数矩阵实现寄存器最小化的重定时
IF 1.7 4区 计算机科学
IEEE Embedded Systems Letters Pub Date : 2024-07-29 DOI: 10.1109/LES.2024.3435388
H. Emmanuel Muñoz;Jorge Rivera;Susana Ortega-Cisneros;Diego H. Gaytán-Rivas
{"title":"On the Retiming for Register Minimization by Means of Breadth Coefficients Matrix","authors":"H. Emmanuel Muñoz;Jorge Rivera;Susana Ortega-Cisneros;Diego H. Gaytán-Rivas","doi":"10.1109/LES.2024.3435388","DOIUrl":"10.1109/LES.2024.3435388","url":null,"abstract":"This letter is focused in the retiming technique for register minimization. This technique was presented as a minimum-cost linear problem, where the use of a fanout gadget was proposed to the model nodes (the functional blocks) in a digital circuit with multiple output edges to obtain a retiming solution <inline-formula> <tex-math>$r(V)$ </tex-math></inline-formula> with integer values. The goal of this technique is to minimize the function <inline-formula> <tex-math>${mathrm { COST}}^{prime } =sum _{e} beta (e)omega _{r} (e)$ </tex-math></inline-formula> subject to feasibility and clock period constraints. The determination of the breadth coefficients <inline-formula> <tex-math>$beta (e)$ </tex-math></inline-formula> could be cumbersome for large digital circuits, as there is no suitable method in the literature. Based on some concepts from graph theory and linear algebra, an algorithm for computing the breadth coefficients is proposed. An example is presented in order to illustrate the performance of the proposed algorithm as calculations for the breadth coefficients are effortless determined.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"17 1","pages":"58-61"},"PeriodicalIF":1.7,"publicationDate":"2024-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141871021","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Hardware-Aware Bayesian Neural Architecture Search of Quantized CNNs 量化 CNN 的硬件感知贝叶斯神经架构搜索
IF 1.7 4区 计算机科学
IEEE Embedded Systems Letters Pub Date : 2024-07-26 DOI: 10.1109/LES.2024.3434379
Mathieu Perrin;William Guicquero;Bruno Paille;Gilles Sicard
{"title":"Hardware-Aware Bayesian Neural Architecture Search of Quantized CNNs","authors":"Mathieu Perrin;William Guicquero;Bruno Paille;Gilles Sicard","doi":"10.1109/LES.2024.3434379","DOIUrl":"10.1109/LES.2024.3434379","url":null,"abstract":"Advances in neural architecture search (NAS) now provide a crucial assistance to design hardware-efficient neural networks (NNs). This letter presents NAS for resource-efficient, weight-quantized convolutional NNs (CNNs), under computational complexity constraints (model size and number of computations). Bayesian optimization is used to efficiently search for traceable CNN architectures within a continuous embedding space. This embedding is the latent space of a neural architecture autoencoder, regularized with a maximum mean discrepancy penalization and a convex latent predictor of parameters. On CIFAR-100, and without quantization, we obtain 75% test accuracy with less than 2.5M parameters and 600M operations. NAS experiments on STL-10 with 32, 8, and 4 bit weights outperform some high-end architectures while enabling drastic model size reduction (6 Mb–840 kb). It demonstrates our method’s ability to discover lightweight and high-performing models, while showcasing the importance of quantization to improve the tradeoff between accuracy and model size.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"17 1","pages":"42-45"},"PeriodicalIF":1.7,"publicationDate":"2024-07-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141782194","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An Endogenous Security Study of Telematics Box in Intelligent Connected Vehicles 智能网联汽车车载信息箱的内生安全研究
IF 1.7 4区 计算机科学
IEEE Embedded Systems Letters Pub Date : 2024-07-23 DOI: 10.1109/LES.2024.3432593
Zhen Zhang;Yuezhong Zhang;Jinfeng Zhang;Jichao Xie;Shaoxun Liu
{"title":"An Endogenous Security Study of Telematics Box in Intelligent Connected Vehicles","authors":"Zhen Zhang;Yuezhong Zhang;Jinfeng Zhang;Jichao Xie;Shaoxun Liu","doi":"10.1109/LES.2024.3432593","DOIUrl":"10.1109/LES.2024.3432593","url":null,"abstract":"Intelligent connected vehicles (ICVs) are the result of technological advancements in the new era, greatly enhancing the driving experience. However, due to the complex nature of the system, the intelligence of devices, and the connectivity of data, a complex physical fusion system has been created. The in-vehicle Telematics Box (T-Box), serving as the central communication and data hub, faces challenges, such as network vulnerabilities, data privacy, and malicious attacks through untrusted software updates. Therefore, an in-vehicle T-Box with high reliability, security, and performance is an urgent product in the era of the Internet of Vehicles. This article investigates the endogenous security of the T-Box in ICV, with a focus on the integration of dynamic heterogeneous redundancy (DHR) architecture. The underlying idea is to transform the original system into multiple heterogeneous systems, where some of them handle the same business functions. By applying a consensus mechanism to detect malicious nodes and dynamically scheduling healthy nodes into the working mode, a self-purifying defense system with intrinsic security is formed. This design approach endows the T-Box with inherent defense capabilities against unknown vulnerabilities. Meanwhile, the in-vehicle T-Box is redesigned in the software and hardware implementation scheme. Experimental results demonstrate that the new design notably enhances and ensures the robust stability and elevated reliability of the in-vehicle T-Box. Evidently, the upgraded T-Box ensures the safe processing of in-vehicle CAN bus data.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 4","pages":"501-504"},"PeriodicalIF":1.7,"publicationDate":"2024-07-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141782193","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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