IEEE Embedded Systems Letters最新文献_第6页

Reliable Methodology to FPGA Design Verification and Noise Analysis for Digital Lock-In Amplifiers 数字锁相放大器 FPGA 设计验证和噪声分析的可靠方法

IF 1.7 4区计算机科学

IEEE Embedded Systems Letters Pub Date : 2024-06-18 DOI: 10.1109/LES.2024.3415651

Jose Alejandro Galaviz-Aguilar;Cesar Vargas-Rosales;Francisco Falcone

{"title":"Reliable Methodology to FPGA Design Verification and Noise Analysis for Digital Lock-In Amplifiers","authors":"Jose Alejandro Galaviz-Aguilar;Cesar Vargas-Rosales;Francisco Falcone","doi":"10.1109/LES.2024.3415651","DOIUrl":"10.1109/LES.2024.3415651","url":null,"abstract":"The lock-in amplifier (LIA) instruments are designed to provide signal conditioning for precision measurement systems to extract signals from extremely noisy environments. The digital LIAs design often requires a verification process to ensure hardware performance. Thus, hardware description language (HDL) with functional verification strategies offers a powerful tool to provide an field-programmable gate array (FPGA) integrated solution. In this letter, we propose a methodology of design and verification of all-digital LIA and an additive white Gaussian noise (AWGN) module able to measure extremely lower levels of signal-to-noise ratio (SNR) of \u0000<inline-formula> <tex-math>$approx $ </tex-math></inline-formula>\u0000 \u0000<inline-formula> <tex-math>${10}^{-{15}}$ </tex-math></inline-formula>\u0000 or down to −37 dB while a wide reserve of spurious-free dynamic range (SFDR) up to 90 dB on FPGA is ensured. To this end, the designed and implemented FPGA framework for quick, accurate, and comprehensive characterization of a given digital LIA is used to leverage the capabilities of the design under controllable AWGN noise patterns stimulus.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 3","pages":"307-310"},"PeriodicalIF":1.7,"publicationDate":"2024-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141937441","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Virtually Contiguous Memory Allocation in Embedded Systems: A Performance Analysis 嵌入式系统中的虚拟连续内存分配：性能分析

IF 1.6 4区计算机科学

IEEE Embedded Systems Letters Pub Date : 2024-06-18 DOI: 10.1109/les.2024.3416192

Yacine Hadjadj, Chakib Mustapha Anouar Zouaoui, Nasreddine Taleb

引用次数: 0

76.5-Gbps Viterbi Decoder for Convolutional Codes on GPU GPU 上用于卷积码的 76.5-Gbps Viterbi 译码器

IF 1.6 4区计算机科学

IEEE Embedded Systems Letters Pub Date : 2024-06-18 DOI: 10.1109/les.2024.3416401

Zhanxian Liu, Chufan Liu, Haijun Zhang, Ling Zhao

引用次数: 0

Wireless Tag Sensor Network for Apnea Detection and Posture Recognition Using LSTM 利用 LSTM 进行呼吸暂停检测和姿势识别的无线标签传感器网络

IF 1.7 4区计算机科学

IEEE Embedded Systems Letters Pub Date : 2024-06-14 DOI: 10.1109/LES.2024.3410024

Rafik Saddaoui;Massine Gana;Hamid Hamiche;Mourad Laghrouche

{"title":"Wireless Tag Sensor Network for Apnea Detection and Posture Recognition Using LSTM","authors":"Rafik Saddaoui;Massine Gana;Hamid Hamiche;Mourad Laghrouche","doi":"10.1109/LES.2024.3410024","DOIUrl":"10.1109/LES.2024.3410024","url":null,"abstract":"We have developed a low-cost, high-accuracy, and energy-efficient wearable tag sensor for apnea detection. The sensor can detect different types of breathing problems by monitoring the small movements of the chest wall compartments during each respiration cycle. This tag sensor sends also apnea events, digital respiration rate, and patient posture data using an ultra high radio frequency identification (UHF RFID) reader. The reader is based on the recent AS3993 chip connected to a Raspberry Pi 4 controller, which acts as a local server and is connected to the cloud to share acquired data with the treating doctor. A sleep disorder detection and classification with several positions using a long short-term memory (LSTM) network algorithm is implemented in real-time on the embedded arm microcontroller STM32F407. The proposed apnea detection method exhibits low error, enabling it to meet clinical requirements. The accuracy of apnea events and position detection were triggered in over 93% of cases. We have also evaluated six different classification techniques optimized by considering the proposed feature extraction and regularization of classifier parameters.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 4","pages":"469-472"},"PeriodicalIF":1.7,"publicationDate":"2024-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141937444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Evaluating NTT/INTT Implementation Styles for Post-Quantum Cryptography 评估后量子密码学的 NTT/INTT 实现风格

IF 1.7 4区计算机科学

IEEE Embedded Systems Letters Pub Date : 2024-06-06 DOI: 10.1109/LES.2024.3410516

Malik Imran;Safiullah Khan;Ayesha Khalid;Ciara Rafferty;Yasir Ali Shah;Samuel Pagliarini;Muhammad Rashid;Máire O’Neill

{"title":"Evaluating NTT/INTT Implementation Styles for Post-Quantum Cryptography","authors":"Malik Imran;Safiullah Khan;Ayesha Khalid;Ciara Rafferty;Yasir Ali Shah;Samuel Pagliarini;Muhammad Rashid;Máire O’Neill","doi":"10.1109/LES.2024.3410516","DOIUrl":"10.1109/LES.2024.3410516","url":null,"abstract":"Unifying the forward and inverse operations of the number theoretic transform (NTT) into a single hardware module is a common practice when designing polynomial coefficient multiplier accelerators as used in the post-quantum cryptographic algorithms. This letter experimentally evaluates that this design unification is not always advantageous. In this context, we present three NTT hardware architectures: 1) a forward NTT (FNTT) architecture; 2) an inverse NTT (INTT) architecture; and 3) a unified NTT (UNTT) architecture for computing the FNTT and INTT computations on a single design. We benchmark our throughput/area and energy/area evaluations on Xilinx Virtex-7 field-programmable gate array (FPGA) and 28-nm application-specific integrated circuit (ASIC) platforms. The standalone FNTT and INTT designs, on average on FPGA, exhibit \u0000<inline-formula> <tex-math>$4.66times $ </tex-math></inline-formula>\u0000 and \u0000<inline-formula> <tex-math>$3.75times $ </tex-math></inline-formula>\u0000 higher throughput/area and energy/area values, respectively, than the UNTT design. Similarly, the individual FNTT and INTT designs, on average on ASIC, achieve \u0000<inline-formula> <tex-math>$1.25times $ </tex-math></inline-formula>\u0000 and \u0000<inline-formula> <tex-math>$1.09times $ </tex-math></inline-formula>\u0000 higher throughput/area and energy/area values, respectively, compared to the UNTT design.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 4","pages":"485-488"},"PeriodicalIF":1.7,"publicationDate":"2024-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141937516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

FEARLESS: A Federated Reinforcement Learning Orchestrator for Serverless Edge Swarms 无畏：无服务器边缘群的联合强化学习协调器

IF 1.6 4区计算机科学

IEEE Embedded Systems Letters Pub Date : 2024-06-06 DOI: 10.1109/les.2024.3410892

Christos Sad, Dimosthenis Masouros, Kostas Siozios

引用次数: 0

Speed Record of AES-CTR and AES-ECB Bit-Sliced Implementation on GPUs 在 GPU 上实现 AES-CTR 和 AES-ECB 比特切分的速度记录

IF 1.7 4区计算机科学

IEEE Embedded Systems Letters Pub Date : 2024-06-05 DOI: 10.1109/LES.2024.3409725

Wai-Kong Lee;Seog Chung Seo;Hwajeong Seo;Dong Cheon Kim;Seong Oun Hwang

引用次数: 0

Marine Monitoring System Powered by Flexible Solar Panel 由柔性太阳能电池板供电的海洋监测系统

IF 1.6 4区计算机科学

IEEE Embedded Systems Letters Pub Date : 2024-05-09 DOI: 10.1109/les.2024.3396061

C. Antonio-Hernández, F. López-Huerta, J. Figueroa-Moo, L.N. Acquaroli, E. Osorio-de-la-Rosa

引用次数: 0

LoRa, Sigfox, and NB-IoT: An Empirical Comparison for IoT LPWAN Technologies in the Agribusiness LoRa、Sigfox 和 NB-IoT：农业综合企业物联网 LPWAN 技术的经验比较

IF 1.7 4区计算机科学

IEEE Embedded Systems Letters Pub Date : 2024-04-29 DOI: 10.1109/LES.2024.3394446

Juan Pablo Becoña;Marcel Grané;Matías Miguez;Alfredo Arnaud

引用次数: 0

Improving Netlist Transformation-Based Approximate Logic Synthesis Through Resynthesis 通过重合成改进基于网表转换的近似逻辑合成

IF 1.7 4区计算机科学

IEEE Embedded Systems Letters Pub Date : 2024-04-18 DOI: 10.1109/LES.2024.3391220

Roger Morales-Monge;Jorge Castro-Godínez;Guilherme Paim

引用次数: 0