An Optimized Structure for Data Alignment Logic in Parallel CRC Computing Circuits

Abstract

In bit-level parallel cyclic redundancy check (CRC) computing circuits, it is possible that the input data length may not be evenly divisible by the parallel bit width. Consequently, the incorporation of alignment logic into the circuit is necessary to discard the invalid data. A comprehensive analysis of 256-bits parallel circuits reveals that the data alignment structure introduces an additional delay of 46% to 53.8%. We proposed a prealignment structure as a means of optimizing the data alignment logic. This structure separates the data alignment logic from the loopback structure generated by the parallel computing logic, allowing for pipelining between the data alignment logic and the parallel computing logic. On-board tests on field-programmable gate arrays (FPGAs) show that circuits with a prealignment structure have an increase in maximum clock frequency of about 95% to 175% and a reduction in average energy consumption for computation of about 40.6% to 55% compared to circuits using a shift-alignment structure.