{"title":"HTree: Hardware Trojan Attack on Cache Resizing Policies","authors":"Atul Kumar;Shirshendu Das;Basant Subba","doi":"10.1109/LES.2023.3347607","DOIUrl":"https://doi.org/10.1109/LES.2023.3347607","url":null,"abstract":"Modern chipmultiprocessors (CMPs) use third-party intellectual properties (IPs) to reduce design costs and meet deadlines. The cores in the CMP has their own private cache memories and all the cores share a common large sized last level cache (LLC). All the components of CMP, including cores and cache memories, are connected through a network-on-chip (NoC). Most of the NoC components have third-party IPs. Some of these IPs may be malicious and act as Hardware Trojan (HT). In this letter, we propose an HT-base attack that targets the LLC resizing techniques. The LLC resizing techniques are used to reduce the energy consumption of the LLC by shutting down unused parts of the LLC. The proposed attack can misuse the properties of these resizing techniques to reduce their energy saving up to 58%. The proposed attack can also reduce the system performance up to 18%.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 3","pages":"263-266"},"PeriodicalIF":1.7,"publicationDate":"2023-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142091015","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Coelho;L. Santiago;D. Araújo;A. Navarro;N. B. Carvalho
{"title":"A Low-Cost Embedded System to Support Broadcasting Emergency Messages Through FM Radio Stations","authors":"M. Coelho;L. Santiago;D. Araújo;A. Navarro;N. B. Carvalho","doi":"10.1109/LES.2023.3343641","DOIUrl":"https://doi.org/10.1109/LES.2023.3343641","url":null,"abstract":"Emergency alert systems (EASs) have been deployed in some countries in order to broadcast emergency alerts and warning messages to the public. In this letter, we describe an innovative electronic embedded solution, named Firetec switch, intended to be placed in the FM radio stations. This switch will be supported by a server placed at the authorized officials, with the capability to generate the audio alerting messages. One interesting challenge is to deliver the messages only to the local public, in the catastrophe neighborhood, by using FM radio stations. This letter focuses on the description of the Firetec switch hardware and software.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 3","pages":"247-250"},"PeriodicalIF":1.7,"publicationDate":"2023-12-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142091007","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Xochitl Maya;Adrián E. Soto;Ángel A. Vázquez;Juan G. Avalos;Giovanny Sanchez;Juan C. Sánchez
{"title":"A New Switching MVC Algorithm for Active Impulsive Noise Control","authors":"Xochitl Maya;Adrián E. Soto;Ángel A. Vázquez;Juan G. Avalos;Giovanny Sanchez;Juan C. Sánchez","doi":"10.1109/LES.2023.3343293","DOIUrl":"https://doi.org/10.1109/LES.2023.3343293","url":null,"abstract":"In realistic sound scenarios, cutting-edge active noise control (ANC) systems still suffer critical instabilities since these systems works under impulsive noise signals. To decrease the negative impact of this noise, several authors have made extraordinary efforts to develop efficient algorithms in terms of convergence speed and misadjustment. However, these algorithms still exhibits limited convergence capabilities. In this letter, we present for the first time, the development of a switching algorithm based on the maximum versoria criterion (MVC) algorithm. Our results demonstrate that the proposed switching algorithm exhibits good convergence properties while maintaining a lower-computational cost when compared with existing algorithms.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 3","pages":"271-274"},"PeriodicalIF":1.7,"publicationDate":"2023-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142090694","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Romina Soledad Molina;Iván René Morales;Maria Liz Crespo;Veronica Gil Costa;Sergio Carrato;Giovanni Ramponi
{"title":"An End-to-End Workflow to Efficiently Compress and Deploy DNN Classifiers on SoC/FPGA","authors":"Romina Soledad Molina;Iván René Morales;Maria Liz Crespo;Veronica Gil Costa;Sergio Carrato;Giovanni Ramponi","doi":"10.1109/LES.2023.3343030","DOIUrl":"https://doi.org/10.1109/LES.2023.3343030","url":null,"abstract":"Machine learning (ML) models have demonstrated discriminative and representative learning capabilities over a wide range of applications, even at the cost of high-computational complexity. Due to their parallel processing capabilities, reconfigurability, and low-power consumption, systems on chip based on a field programmable gate array (SoC/FPGA) have been used to face this challenge. Nevertheless, SoC/FPGA devices are resource-constrained, which implies the need for optimal use of technology for the computation and storage operations involved in ML-based inference. Consequently, mapping a deep neural network (DNN) architecture to a SoC/FPGA requires compression strategies to obtain a hardware design with a good compromise between effectiveness, memory footprint, and inference time. This letter presents an efficient end-to-end workflow for deploying DNNs on an SoC/FPGA by integrating hyperparameter tuning through Bayesian optimization (BO) with an ensemble of compression techniques.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 3","pages":"255-258"},"PeriodicalIF":1.7,"publicationDate":"2023-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142091036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Woosuk Kang;EunJin Jeong;Kyonghwan Yoon;Soonhoi Ha
{"title":"Software Synthesis From High-Level Specification for Swarm Robotic Applications","authors":"Woosuk Kang;EunJin Jeong;Kyonghwan Yoon;Soonhoi Ha","doi":"10.1109/LES.2023.3339159","DOIUrl":"https://doi.org/10.1109/LES.2023.3339159","url":null,"abstract":"Programming for swarm robots is challenging due to platform diversity and the gap between individual and swarm behaviors. To tackle this challenge, we propose a component-based software synthesis method from a high-level specification. To support heterogeneous robots and maximize code reuse, we adopt a component-based approach that classifies software components into three categories: 1) robot; 2) algorithm; and 3) consensus. We generate a task graph model for an individual robot from a high-level specification and use a software synthesizer to generate the target code from the task graph model. Through a proof-of-concept implementation with a group searching application, the viability of the proposed technique is demonstrated.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 3","pages":"243-246"},"PeriodicalIF":1.7,"publicationDate":"2023-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142090708","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
V. Bala Naga Jyothi;S. Jai Akash;G. Ananda Ramadass;N. Vedachalam;Hrishikesh Venkataraman
{"title":"Design and Development of Deep Learning-Aided Vision Guidance System for AUV Homing Applications","authors":"V. Bala Naga Jyothi;S. Jai Akash;G. Ananda Ramadass;N. Vedachalam;Hrishikesh Venkataraman","doi":"10.1109/LES.2023.3339145","DOIUrl":"https://doi.org/10.1109/LES.2023.3339145","url":null,"abstract":"In the current subsea industry scenario, autonomous underwater vehicles (AUVs) are widely used for expeditions and explorations. However, the mission duration is limited due to the limitations in the battery capacity. To increase the endurance, there is a need for a submerged docking station (DS) to charge the battery, also to update the next mission profile. In this letter, deep learning (DL) technique aided short-range vision guidance is envisaged for a reliable and precise AUV homing operation. Intelligent control algorithms with an efficient DL-based you only look once (YOLO) v5-image processing techniques are used for DS detection and tracking and deployed in an edge computer integrated into AUV prototype. The developed illuminated DS and AUV prototype with high-definition camera has been demonstrated in test tank at depth of 2 m. An analysis was conducted on the DS data set, which comprised 132 images of clear and turbid water, 13 were designated for testing, 40 for validation, and 79 for training purposes. The results were observed that the probability of detecting the DS is 95%, detection range is 5 m, the probability of homing toward the DS is CEP 90 with the position error of 5% in less-turbid waters and in high-turbid waters, 60% is the probability of DS detection with position error up to 25%, detectable range is 1 m. The proposed embedded hardware is extremely useful for underwater reliable homing applications.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 2","pages":"198-201"},"PeriodicalIF":1.6,"publicationDate":"2023-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141182041","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"ML-Based Trojan Classification: Repercussions of Toxic Boundary Nets","authors":"Saleh Mulhem;Felix Muuss;Christian Ewert;Rainer Buchty;Mladen Berekovic","doi":"10.1109/LES.2023.3338543","DOIUrl":"https://doi.org/10.1109/LES.2023.3338543","url":null,"abstract":"Machine learning (ML) algorithms were recently adapted for testing integrated circuits and detecting potential design backdoors. Such testing mechanisms mainly rely on the available training dataset and the extracted features of the Trojan circuit. In this letter, we demonstrate that this method is attackable by exploiting a structural problem of classifiers for hardware Trojan (HT) detection in gate-level netlists, called the boundary net (BN) problem. There, an adversary modifies the labels of those BNs, connecting the original logic to the Trojan circuit. We show that the proposed adversarial label-flipping attacks (ALFAs) are potentially highly toxic to the accuracy of supervised ML-based Trojan detection approaches. The experimental results indicate that an adversary needs to flip only 0.09% of all labels to achieve an accuracy drop of over 9%, demonstrating one of the most efficient ALFAs in the HT detection research domain.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 3","pages":"251-254"},"PeriodicalIF":1.7,"publicationDate":"2023-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10341539","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142091016","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Cost-Effective Indoor Surveillance System With Multihop Router Network","authors":"Debajyoti Biswas;Suvankar Barai","doi":"10.1109/LES.2023.3337432","DOIUrl":"https://doi.org/10.1109/LES.2023.3337432","url":null,"abstract":"In this letter, a cost-effective sensing-capable multihop router network architecture has been designed for the hotel indoor surveillance system with the help of wemos D1 R2, Arduino Mega, relays, and sensors (WARS). To make each router, there are mainly three components, i.e., one access point (AP), one station (STA), and one controller. These components have different working functionalities. Though we have focused on hotel surveillance systems but the network will be useful for broad application purposes, including home, hospital, restaurant, agriculture, etc., according to the requirement of sensors. To regulate the information of the sensor, a smartphone application (APP) has been designed. With this architecture, the proposed multihop network can increase the regularity performance of the hotel without violating customers’ privacy.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 2","pages":"218-221"},"PeriodicalIF":1.6,"publicationDate":"2023-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141181889","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Multistage Multirate Filterbank for FPGA Resource Optimization","authors":"L. H. Arnaldi","doi":"10.1109/LES.2023.3337323","DOIUrl":"https://doi.org/10.1109/LES.2023.3337323","url":null,"abstract":"In this letter, the problem of optimization of multirate filterbanks is addressed. The factors that define the efficiency of these multirate systems are investigated and the implementations of structures in stages are analyzed. The latter, together with the polyphase implementations of the filters, allows obtaining optimal filterbanks in the use of resources for the FPGAs.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 3","pages":"259-262"},"PeriodicalIF":1.7,"publicationDate":"2023-11-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142090899","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}