IEEE Embedded Systems Letters最新文献_第9页

Real-Time Tomato Quality Assessment Using Hybrid CNN-SVM Model 使用混合 CNN-SVM 模型实时评估番茄质量

IF 1.7 4区计算机科学

IEEE Embedded Systems Letters Pub Date : 2024-02-27 DOI: 10.1109/LES.2024.3370634

Hassan Shabani Mputu;Ahmed-Abdel Mawgood;Atsushi Shimada;Mohammed S. Sayed

{"title":"Real-Time Tomato Quality Assessment Using Hybrid CNN-SVM Model","authors":"Hassan Shabani Mputu;Ahmed-Abdel Mawgood;Atsushi Shimada;Mohammed S. Sayed","doi":"10.1109/LES.2024.3370634","DOIUrl":"10.1109/LES.2024.3370634","url":null,"abstract":"The current quality assessment for fruits and vegetables relies on subjective human judgment and manual inspection, resulting in inconsistencies and inefficiencies. Due to that, there is a need for a real-time system that can accurately and efficiently assess the quality of fruits and vegetables by analyzing various parameters, such as color, texture, size, and blemishes, to ensure consistency and reduce waste in the food supply chain. This study presents the development of a real-time tomato classification system using a hybrid model that combines convolutional neural network (CNN) and support vector machines (SVMs) deployed on the embedded single-board NVIDIA Jetson TX1. The selected CNN model EfficientNetB0 was used for feature extraction and SVM for classification. Notably, the EfficientNetB0-SVM hybrid model demonstrated impressive efficiency, achieving an average accuracy of 93.54% for classifying static tomato images stored in a board into healthy or reject with a testing time of 0.0216-s per image. Also, during real-time implementation, the proposed hybrid model attained an average inference speed of 15.6 frames per second (15.6 FPS), with an accuracy of 78.57% in classifying actual tomatoes into healthy or reject. The classification decision was taken based on 5 images for each tomato captured at different angles to ensure the detection of any blemishes from almost all sides of the tomato. The performance of the proposed model outperforms that of the state-of-the-art (SOTA) methods in accuracy, testing time per image, and real-time prediction accuracy.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 4","pages":"453-456"},"PeriodicalIF":1.7,"publicationDate":"2024-02-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140003877","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

High-Speed Energy-Efficient Fixed-Point Signed Multipliers for FPGA-Based DSP Applications 基于 FPGA 的 DSP 应用中的高速节能定点有符号乘法器

IF 1.7 4区计算机科学

IEEE Embedded Systems Letters Pub Date : 2024-02-12 DOI: 10.1109/LES.2024.3364698

Mitul Sudhirkumar Nagar;Aditya Mathuriya;Sohan H. Patel;Pinalkumar J. Engineer

{"title":"High-Speed Energy-Efficient Fixed-Point Signed Multipliers for FPGA-Based DSP Applications","authors":"Mitul Sudhirkumar Nagar;Aditya Mathuriya;Sohan H. Patel;Pinalkumar J. Engineer","doi":"10.1109/LES.2024.3364698","DOIUrl":"10.1109/LES.2024.3364698","url":null,"abstract":"Among various platforms for computer vision algorithms, FPGA has gained popularity as a low-power solution. These algorithms involve convolution operation which are extensively performed using signed multipliers. Hence, this work proposes high-speed and energy-efficient signed fixed-point multipliers for digital signal processing (DSP) applications. This work focuses on reducing the combinational path delay (CPD) using LUT-based Booth radix-4 partial product (PP) generation with Bewick’s sign extension and Dadda-based concurrent PP reduction with carry save adder (CSA) for Xilinx (now AMD) FPGA. The proposed design eliminates the requirement of a long carry chain for PP reduction. The proposed multiplier reduces CPD by 3%, 4%, and 16% compared to the state-of-the-art (SoA) multiplier for \u0000<inline-formula> <tex-math>$8times 8$ </tex-math></inline-formula>\u0000, \u0000<inline-formula> <tex-math>$16times 16$ </tex-math></inline-formula>\u0000, and \u0000<inline-formula> <tex-math>$32times 32$ </tex-math></inline-formula>\u0000 sizes, respectively. We have also analyzed our proposed \u0000<inline-formula> <tex-math>$32times 32$ </tex-math></inline-formula>\u0000 multiplier by pipelining, which offers CPD and EDP reduction by 12.28% and 19.47% at the cost of a 3% and 80% increase in LUTs and flip-flops, respectively, compared to the combinatorial multiplier.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 4","pages":"417-420"},"PeriodicalIF":1.7,"publicationDate":"2024-02-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139954504","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

LOTUS: A Scalable Framework to Lock Multimodule Designs With One-Time Self-Destructing Key LOTUS：利用一次性密钥和自毁方法锁定多模块设计的可扩展框架

IF 1.7 4区计算机科学

IEEE Embedded Systems Letters Pub Date : 2024-02-05 DOI: 10.1109/LES.2024.3360615

Mona Hashemi;Siamak Mohammadi;Trevor E. Carlson

引用次数: 0

ProMiSE: A Programmable Hardware Monitor for Secure Execution in Zero Trust Networks PROMISE：零信任网络中安全执行的可编程硬件监控器

IF 1.7 4区计算机科学

IEEE Embedded Systems Letters Pub Date : 2024-01-16 DOI: 10.1109/LES.2024.3354831

Nikhilesh Singh;Shagnik Pal;Rainer Leupers;Farhad Merchant;Chester Rebeiro

引用次数: 0

Middleton Class A Noise Median Estimator: FPGA and Software Implementation Middleton A 级噪声中值估计器：FPGA 和软件实现

IF 1.7 4区计算机科学

IEEE Embedded Systems Letters Pub Date : 2024-01-15 DOI: 10.1109/LES.2024.3354179

Lucas A. Rabioglio;M. C. Cebedio;L. Arnone;L. De Micco;J. Castiñeira Moreira

引用次数: 0

SoC-Based Implementation of 1-D Convolutional Neural Network for 3-Channel ECG Arrhythmia Classification via HLS4ML 通过 HLS4ML 实现基于 SoC 的用于 3 通道心电图心律失常分类的一维卷积神经网络

IF 1.7 4区计算机科学

IEEE Embedded Systems Letters Pub Date : 2024-01-15 DOI: 10.1109/LES.2024.3354081

Feroz Ahmad;Saima Zafar

{"title":"SoC-Based Implementation of 1-D Convolutional Neural Network for 3-Channel ECG Arrhythmia Classification via HLS4ML","authors":"Feroz Ahmad;Saima Zafar","doi":"10.1109/LES.2024.3354081","DOIUrl":"10.1109/LES.2024.3354081","url":null,"abstract":"Real-time monitoring of 1-D biopotentials, such as electrocardiograms (ECG), necessitates effective feature extraction and classification, a strength of deep learning (DL) algorithms. Designing 1-D convolutional neural network (1-D CNN) accelerators for biopotential classification via open-source codesign workflows, particularly high-level synthesis for machine learning (HLS4ML), offers advantages over GPU-based or cloud-based solutions, including high performance, low latency, low power consumption, swift time-to-market, and cost-effectiveness. We present an implementation of a quantized-pruned (QP) 1-D CNN model on the PYNQ Z2 SoC using HLS4ML by seamlessly deploying its soft IP core generated via Vivado Accelerator backend, showcasing the efficacy of quantization-aware training (QAT) in reducing power consumption to 1.655 W from 1.823 W. Our approach demonstrates improved area consumption, resource utilization, and inferences per second compared to the baseline (B) 1-D CNN model, with a controlled 4% or less reduction in weighted Accuracy, Precision, Recall, and F1-score, revealing the nuanced tradeoffs between performance metrics and system efficiency for real-time 3-channel ECG Arrhythmia classification.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 4","pages":"429-432"},"PeriodicalIF":1.7,"publicationDate":"2024-01-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139954458","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An Area and Energy Efficient Serial-Multiplier 面积和能效比高的串行乘法器

IF 1.7 4区计算机科学

IEEE Embedded Systems Letters Pub Date : 2024-01-10 DOI: 10.1109/LES.2024.3352540

Mohd. Tasleem Khan;Jinti Hazarika

引用次数: 0

Adaptive Kernel Merge and Fusion for Multi-Tenant Inference in Embedded GPUs 嵌入式 GPU 多租户推理的自适应内核合并与融合

IF 1.7 4区计算机科学

IEEE Embedded Systems Letters Pub Date : 2024-01-09 DOI: 10.1109/LES.2024.3351753

Jaebeom Jeon;Gunjae Koo;Myung Kuk Yoon;Yunho Oh

{"title":"Adaptive Kernel Merge and Fusion for Multi-Tenant Inference in Embedded GPUs","authors":"Jaebeom Jeon;Gunjae Koo;Myung Kuk Yoon;Yunho Oh","doi":"10.1109/LES.2024.3351753","DOIUrl":"10.1109/LES.2024.3351753","url":null,"abstract":"This letter proposes a new scheme that improves throughput and reduces queuing delay while running multiple inferences in embedded graphics processing unit (GPU)-based systems. We observe that an embedded system runs inference with a fixed number of deep learning models and that inference requests often use the same model. Unlike prior work that proposed kernel fusion or scheduling techniques, this letter proposes a new software technique that merges and fuses kernels by monitoring the requests in a queue. The proposed technique first monitors a fixed number of requests and groups the requests running the same model. Then, it creates the kernels that iteratively process the grouped requests. We call such a technique kernel merging. After that, the proposed technique performs kernel fusion with merged kernels. Eventually, our idea minimizes the number of concurrent kernels, thus mitigating stalls caused by frequent context switching in a GPU. In our evaluation, the proposed kernel merge and fusion achieve \u0000<inline-formula> <tex-math>$2.7times $ </tex-math></inline-formula>\u0000 better throughput, 47% shorter average kernel execution time, and 63% shorter tail latency than prior work.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 4","pages":"421-424"},"PeriodicalIF":1.7,"publicationDate":"2024-01-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139954771","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Controlling a House’s Air-Conditioning Using Nonlinear Model Predictive Control 利用非线性模型预测控制来控制房屋空调系统

IF 1.6 4区计算机科学

IEEE Embedded Systems Letters Pub Date : 2024-01-04 DOI: 10.1109/LES.2023.3348705

Bashra Kadhim Oleiwi;Ahmad H. Sabry

引用次数: 0

DATA: Throughput and Deadline-Aware Genetic Approach for Task Scheduling in Fog Networks DATA：用于雾网络任务调度的吞吐量和截止时间感知遗传方法

IF 1.7 4区计算机科学

IEEE Embedded Systems Letters Pub Date : 2023-12-29 DOI: 10.1109/LES.2023.3348499

Arya Motamedhashemi;Bardia Safaei;Amir Mahdi Hosseini Monazzah;Alireza Ejlali

{"title":"DATA: Throughput and Deadline-Aware Genetic Approach for Task Scheduling in Fog Networks","authors":"Arya Motamedhashemi;Bardia Safaei;Amir Mahdi Hosseini Monazzah;Alireza Ejlali","doi":"10.1109/LES.2023.3348499","DOIUrl":"10.1109/LES.2023.3348499","url":null,"abstract":"Fog devices in fog computing frameworks are responsible for fetching and executing the tasks submitted by the deployed resource-constraint embedded edge devices. Based on the availability of resources, tasks are offloaded to the virtual machines hosted by the fog devices. These tasks may then get scheduled to guarantee a number of efficiency-related metrics. While throughput has a decisive impact on the timely execution of tasks, the appropriate utilization of this metric has not been considered in the existing mechanisms. In this letter, we first discuss the proper use of this objective in the fitness function of meta-heuristic algorithms. Then, we explain that adopting throughput by the fitness functions in the form of two conventionally used weighted-sum, and fractional techniques may ignore solutions with a better guarantee ratio. Consequently, we propose a novel approach called DATA to be replaced with these two old approaches. DATA is a throughput, and deadline-aware task scheduling mechanism for time-sensitive fog frameworks, which its fitness function utilizes genetic optimization by encoding the solutions into chromosomes. It uses single-gene mutation and two-point crossover. In this approach, two populations are considered to search the problem space. The main population is evaluated based on the guarantee ratio, while the helper population is evaluated based on the throughput. Furthermore, the helper population uses weighted-sum. The initial population is generated randomly by the uniform distribution, to provide a load-balancing. Based on our extensive evaluations, the selected solution by DATA provides the highest guarantee ratio, while having the lowest possible makespan.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 4","pages":"409-412"},"PeriodicalIF":1.7,"publicationDate":"2023-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142199417","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0