IEEE Embedded Systems Letters最新文献_第9页

External Timed I/O Semantics Preserving Utilization Optimization for LET-Based Effect Chain 基于let效应链的外部定时I/O语义保持利用率优化

IF 1.6 4区计算机科学

IEEE Embedded Systems Letters Pub Date : 2023-09-25 DOI: 10.1109/LES.2023.3298741

Bo Zhang;Caixu Zhao;Xi Li

引用次数: 0

Flipping Bits Like a Pro: Precise Rowhammering on Embedded Devices 像专业人士一样翻转比特:在嵌入式设备上精确地滚动

IF 1.6 4区计算机科学

IEEE Embedded Systems Letters Pub Date : 2023-09-25 DOI: 10.1109/LES.2023.3298737

Anandpreet Kaur;Pravin Srivastav;Bibhas Ghoshal

引用次数: 1

Differentiable Slimming for Memory-Efficient Transformers 内存高效变压器的可微分瘦身

IF 1.6 4区计算机科学

IEEE Embedded Systems Letters Pub Date : 2023-09-25 DOI: 10.1109/LES.2023.3299638

Nikolay Penkov;Konstantinos Balaskas;Martin Rapp;Joerg Henkel

{"title":"Differentiable Slimming for Memory-Efficient Transformers","authors":"Nikolay Penkov;Konstantinos Balaskas;Martin Rapp;Joerg Henkel","doi":"10.1109/LES.2023.3299638","DOIUrl":"10.1109/LES.2023.3299638","url":null,"abstract":"Transformer models are continuously achieving state-of-the-art performance on a wide range of benchmarks. To meet demanding performance targets, the number of model parameters is continuously increased. As a result, state-of-the-art Transformers require substantial computational resources prohibiting their deployment on consumer-grade hardware. In the literature, overparameterized Transformers are successfully reduced in size with the help of pruning strategies. Existing works lack the ability to optimize the full architecture, without incurring significant overheads, in a fully differentiable manner. Our work proposes a single-stage approach for training a Transformer for memory-efficient inference and various resource-constrained scenarios. Transformer blocks are extended with trainable gate parameters, which attribute importance and control information flow. Their integration into a differentiable pruning-aware training scheme allows the extraction of extremely sparse subnetworks at runtime, with minimal performance degradation. Evaluative pruning results, at the attention head and layer levels, illustrate the memory efficiency of our trained subnetworks under various memory budgets.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"15 4","pages":"186-189"},"PeriodicalIF":1.6,"publicationDate":"2023-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135699987","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

High-Flexibility Designs of Quantized Runtime Reconfigurable Multi-Precision Multipliers 量化运行时可重构多精度乘法器的高灵活性设计

IF 1.6 4区计算机科学

IEEE Embedded Systems Letters Pub Date : 2023-09-25 DOI: 10.1109/LES.2023.3298736

Yuhao Liu;Shubham Rai;Salim Ullah;Akash Kumar

引用次数: 0

Hardware Trojan Detection Method Against Balanced Controllability Trigger Design 针对平衡可控性触发器设计的硬件木马检测方法

IF 1.6 4区计算机科学

IEEE Embedded Systems Letters Pub Date : 2023-09-25 DOI: 10.1109/LES.2023.3318591

Wei-Ting Hsu;Pei-Yu Lo;Chi-Wei Chen;Chin-Wei Tien;Sy-Yen Kuo

引用次数: 0

Effects of Runtime Reconfiguration on PUFs Implemented as FPGA-Based Accelerators 运行时重构对fpga加速puf实现的影响

IF 1.6 4区计算机科学

IEEE Embedded Systems Letters Pub Date : 2023-09-25 DOI: 10.1109/LES.2023.3299214

Hassan Nassar;Lars Bauer;Jörg Henkel

{"title":"Effects of Runtime Reconfiguration on PUFs Implemented as FPGA-Based Accelerators","authors":"Hassan Nassar;Lars Bauer;Jörg Henkel","doi":"10.1109/LES.2023.3299214","DOIUrl":"10.1109/LES.2023.3299214","url":null,"abstract":"Physical unclonable functions (PUFs) are a handy security primitive for resource-constrained devices. They offer an alternative to the resource-intensive classical hash algorithms. Using the IC differences resulting from the fabrication process, PUFs give device-specific outputs (responses) when given the same inputs (challenges). Hence, without using a device-specific key, PUFs can generate device-specific responses. FPGAs are one of the platforms that are heavily studied as a candidate for PUF implementation. The idea is that a PUF that is designed as an HDL code can be used as part of the static design or as a dynamic accelerator. Previous works studied PUF implementation as part of the static design. In contrast to the state-of-the-art, this letter studies PUFs when used as runtime reconfigurable accelerators. In this letter, we find that not all regions of an FPGA are equally suitable for implementing different PUF types. Regions, where clock routing resources exist, are the worst suited for PUF implementation. Moreover, we find out that for certain PUF types, the property of dynamic partial reconfiguration can lead to performance degradation if not applied carefully. When static routing passing through the region increases, the PUF performance degrades significantly.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"15 4","pages":"174-177"},"PeriodicalIF":1.6,"publicationDate":"2023-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135700348","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

FPGA Implementation of Modified SNOW 3G Stream Ciphers Using Fast and Resource Efficient Substitution Box 基于快速资源高效替换盒的改进SNOW 3G流密码的FPGA实现

IF 1.6 4区计算机科学

IEEE Embedded Systems Letters Pub Date : 2023-09-25 DOI: 10.1109/LES.2023.3298743

Sushree Sila P. Goswami;Gaurav Trivedi

{"title":"FPGA Implementation of Modified SNOW 3G Stream Ciphers Using Fast and Resource Efficient Substitution Box","authors":"Sushree Sila P. Goswami;Gaurav Trivedi","doi":"10.1109/LES.2023.3298743","DOIUrl":"10.1109/LES.2023.3298743","url":null,"abstract":"Security plays a vital role in electronic communication, particularly in wireless networks like long term evolution (LTE), where safeguarding data and resources from malicious activities is crucial. Cryptographic algorithms are at the core of security mechanisms, ensuring the protection of sensitive information. While software implementations of these algorithms are relatively straightforward, they often need more speed in real-time applications for communication devices like mobile phones. Consequently, implementation of these cryptographic algorithms as hardware crypto processors becomes necessary. This letter presents a novel implementation of the SNOW3G crypto processor architecture for the 4G LTE security applications, focusing on area, power, and efficiency. The proposed modified SNOW3G architecture utilizes only 0.31% of the available area when implemented on an FPGA Zynq ZC702 and achieves 28.34 efficiency which quantifies as the ratio of throughput to the area. Furthermore, it consumes a total power of 0.142 mW. These low power and area requirements make the design highly suitable for integration into mobile devices, meeting their specific constraints and enabling efficient cryptographic operations.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"15 4","pages":"238-241"},"PeriodicalIF":1.6,"publicationDate":"2023-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135700003","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Vector-Based Dedicated Processor Architecture for Efficient Tracking in VSLAM Systems 基于矢量的VSLAM系统高效跟踪专用处理器体系结构

IF 1.6 4区计算机科学

IEEE Embedded Systems Letters Pub Date : 2023-09-25 DOI: 10.1109/LES.2023.3298900

Dejian Li;Xi Feng;Chongfei Shen;Qi Chen;Lixin Yang;Sihai Qiu;Xin Jin;Meng Liu

引用次数: 0

Optimized Local Path Planner Implementation for GPU-Accelerated Embedded Systems gpu加速嵌入式系统的优化本地路径规划器实现

IF 1.6 4区计算机科学

IEEE Embedded Systems Letters Pub Date : 2023-09-25 DOI: 10.1109/LES.2023.3298733

Filippo Muzzini;Nicola Capodieci;Federico Ramanzin;Paolo Burgio

引用次数: 0

Hardware–Software Co-Optimization of Long-Latency Stochastic Computing 长延迟随机计算的软硬件协同优化

IF 1.6 4区计算机科学

IEEE Embedded Systems Letters Pub Date : 2023-09-25 DOI: 10.1109/LES.2023.3298734

Sercan Aygun;Lida Kouhalvandi;M. Hassan Najafi;Serdar Ozoguz;Ece Olcay Gunes

引用次数: 0