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76.5-Gb/s Viterbi Decoder for Convolutional Codes on GPU GPU 上用于卷积码的 76.5-Gbps Viterbi 译码器
IF 1.7 4区 计算机科学
IEEE Embedded Systems Letters Pub Date : 2024-06-18 DOI: 10.1109/LES.2024.3416401
Zhanxian Liu;Chufan Liu;Haijun Zhang;Ling Zhao
{"title":"76.5-Gb/s Viterbi Decoder for Convolutional Codes on GPU","authors":"Zhanxian Liu;Chufan Liu;Haijun Zhang;Ling Zhao","doi":"10.1109/LES.2024.3416401","DOIUrl":"10.1109/LES.2024.3416401","url":null,"abstract":"This letter presents an optimized Viterbi decoder of convolutional codes on graphics processing unit (GPU) for software defined radio (SDR) platforms. Before the forward process, channel messages are interleaved with coalesced global memory access and the interleaved messages are represented with 4 bits to improve shared memory efficiency. Moreover, we optimize on-chip memory allocations of the forward process to accelerate instruction execution. Excluding the data transfer latency between host and device, the proposed Viterbi decoder achieves 22.2 and 76.5-Gb/s throughput on Tesla V100 and RTX4090, respectively. Compared with related works, the throughput speedups achieved by the proposed decoder are from <inline-formula> <tex-math>$2.06times $ </tex-math></inline-formula> to <inline-formula> <tex-math>$2.93times $ </tex-math></inline-formula>.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"17 1","pages":"22-25"},"PeriodicalIF":1.7,"publicationDate":"2024-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141937443","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Wireless Tag Sensor Network for Apnea Detection and Posture Recognition Using LSTM 利用 LSTM 进行呼吸暂停检测和姿势识别的无线标签传感器网络
IF 1.7 4区 计算机科学
IEEE Embedded Systems Letters Pub Date : 2024-06-14 DOI: 10.1109/LES.2024.3410024
Rafik Saddaoui;Massine Gana;Hamid Hamiche;Mourad Laghrouche
{"title":"Wireless Tag Sensor Network for Apnea Detection and Posture Recognition Using LSTM","authors":"Rafik Saddaoui;Massine Gana;Hamid Hamiche;Mourad Laghrouche","doi":"10.1109/LES.2024.3410024","DOIUrl":"10.1109/LES.2024.3410024","url":null,"abstract":"We have developed a low-cost, high-accuracy, and energy-efficient wearable tag sensor for apnea detection. The sensor can detect different types of breathing problems by monitoring the small movements of the chest wall compartments during each respiration cycle. This tag sensor sends also apnea events, digital respiration rate, and patient posture data using an ultra high radio frequency identification (UHF RFID) reader. The reader is based on the recent AS3993 chip connected to a Raspberry Pi 4 controller, which acts as a local server and is connected to the cloud to share acquired data with the treating doctor. A sleep disorder detection and classification with several positions using a long short-term memory (LSTM) network algorithm is implemented in real-time on the embedded arm microcontroller STM32F407. The proposed apnea detection method exhibits low error, enabling it to meet clinical requirements. The accuracy of apnea events and position detection were triggered in over 93% of cases. We have also evaluated six different classification techniques optimized by considering the proposed feature extraction and regularization of classifier parameters.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 4","pages":"469-472"},"PeriodicalIF":1.7,"publicationDate":"2024-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141937444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Evaluating NTT/INTT Implementation Styles for Post-Quantum Cryptography 评估后量子密码学的 NTT/INTT 实现风格
IF 1.7 4区 计算机科学
IEEE Embedded Systems Letters Pub Date : 2024-06-06 DOI: 10.1109/LES.2024.3410516
Malik Imran;Safiullah Khan;Ayesha Khalid;Ciara Rafferty;Yasir Ali Shah;Samuel Pagliarini;Muhammad Rashid;Máire O’Neill
{"title":"Evaluating NTT/INTT Implementation Styles for Post-Quantum Cryptography","authors":"Malik Imran;Safiullah Khan;Ayesha Khalid;Ciara Rafferty;Yasir Ali Shah;Samuel Pagliarini;Muhammad Rashid;Máire O’Neill","doi":"10.1109/LES.2024.3410516","DOIUrl":"10.1109/LES.2024.3410516","url":null,"abstract":"Unifying the forward and inverse operations of the number theoretic transform (NTT) into a single hardware module is a common practice when designing polynomial coefficient multiplier accelerators as used in the post-quantum cryptographic algorithms. This letter experimentally evaluates that this design unification is not always advantageous. In this context, we present three NTT hardware architectures: 1) a forward NTT (FNTT) architecture; 2) an inverse NTT (INTT) architecture; and 3) a unified NTT (UNTT) architecture for computing the FNTT and INTT computations on a single design. We benchmark our throughput/area and energy/area evaluations on Xilinx Virtex-7 field-programmable gate array (FPGA) and 28-nm application-specific integrated circuit (ASIC) platforms. The standalone FNTT and INTT designs, on average on FPGA, exhibit \u0000<inline-formula> <tex-math>$4.66times $ </tex-math></inline-formula>\u0000 and \u0000<inline-formula> <tex-math>$3.75times $ </tex-math></inline-formula>\u0000 higher throughput/area and energy/area values, respectively, than the UNTT design. Similarly, the individual FNTT and INTT designs, on average on ASIC, achieve \u0000<inline-formula> <tex-math>$1.25times $ </tex-math></inline-formula>\u0000 and \u0000<inline-formula> <tex-math>$1.09times $ </tex-math></inline-formula>\u0000 higher throughput/area and energy/area values, respectively, compared to the UNTT design.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 4","pages":"485-488"},"PeriodicalIF":1.7,"publicationDate":"2024-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141937516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
FEARLESS: A Federated Reinforcement Learning Orchestrator for Serverless Edge Swarms 无畏：无服务器边缘群的联合强化学习协调器
IF 1.7 4区 计算机科学
IEEE Embedded Systems Letters Pub Date : 2024-06-06 DOI: 10.1109/LES.2024.3410892
Christos Sad;Dimosthenis Masouros;Kostas Siozios
{"title":"FEARLESS: A Federated Reinforcement Learning Orchestrator for Serverless Edge Swarms","authors":"Christos Sad;Dimosthenis Masouros;Kostas Siozios","doi":"10.1109/LES.2024.3410892","DOIUrl":"10.1109/LES.2024.3410892","url":null,"abstract":"The rise of edge computing, characterized by swarms of edge devices, marks a significant shift in cloud-edge computing landscapes, moving data processing closer to the source of data generation. However, this paradigm introduces complexities in orchestration, as traditional centralized methods become inadequate for effectively managing distributed, dynamic edge environments. In this letter, we introduce FEARLESS, a distributed orchestration framework tailored for swarms of edge devices. FEARLESS employs a vertical federated reinforcement learning approach to efficiently orchestrate function invocation requests in serverless swarms. Experimental results demonstrate that FEARLESS significantly reduces the quality-of-service violations of the scheduled tasks by up to 57%, compared to a centralized “least-CPU-utilization” and a “local-execution” approach, while it also achieves approximately up to 20% average total energy reduction.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"17 1","pages":"34-37"},"PeriodicalIF":1.7,"publicationDate":"2024-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141937517","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Speed Record of AES-CTR and AES-ECB Bit-Sliced Implementation on GPUs 在 GPU 上实现 AES-CTR 和 AES-ECB 比特切分的速度记录
IF 1.7 4区 计算机科学
IEEE Embedded Systems Letters Pub Date : 2024-06-05 DOI: 10.1109/LES.2024.3409725
Wai-Kong Lee;Seog Chung Seo;Hwajeong Seo;Dong Cheon Kim;Seong Oun Hwang
{"title":"Speed Record of AES-CTR and AES-ECB Bit-Sliced Implementation on GPUs","authors":"Wai-Kong Lee;Seog Chung Seo;Hwajeong Seo;Dong Cheon Kim;Seong Oun Hwang","doi":"10.1109/LES.2024.3409725","DOIUrl":"10.1109/LES.2024.3409725","url":null,"abstract":"The advanced encryption standard (AES) has been widely used to protect digital data in various applications, such as secure IoT communication, files encryption, and pseudorandom number generation. The efficient implementation of AES on parallel architecture, such as graphics processing unit (GPU), has attracted considerable interest over the past decade. These prior studies mainly implemented the AES electronics code book (ECB) and counter (CTR) mode using the table-based approach. In this brief, we set a new speed record of AES-ECB and AES-CTR on GPU based on the proposed bit-sliced implementation techniques. Our implementation achieved 2.6% (ECB) and 9% (CTR) faster than the state-of-the-art table-based implementation on a RTX3080 GPU. Our work evaluated on an embedded GPU (Jetson Orin Nano) can also achieve high throughput at 60 Gb/s, which is 1.9% (ECB) and 7% (CTR) faster than state-of-the-art.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 4","pages":"481-484"},"PeriodicalIF":1.7,"publicationDate":"2024-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141937518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
LoRa, Sigfox, and NB-IoT: An Empirical Comparison for IoT LPWAN Technologies in the Agribusiness LoRa、Sigfox 和 NB-IoT：农业综合企业物联网 LPWAN 技术的经验比较
IF 1.7 4区 计算机科学
IEEE Embedded Systems Letters Pub Date : 2024-04-29 DOI: 10.1109/LES.2024.3394446
Juan Pablo Becoña;Marcel Grané;Matías Miguez;Alfredo Arnaud
{"title":"LoRa, Sigfox, and NB-IoT: An Empirical Comparison for IoT LPWAN Technologies in the Agribusiness","authors":"Juan Pablo Becoña;Marcel Grané;Matías Miguez;Alfredo Arnaud","doi":"10.1109/LES.2024.3394446","DOIUrl":"10.1109/LES.2024.3394446","url":null,"abstract":"In this letter, three battery-powered, custom Internet of Things (IoT) sensor nodes for the agribusiness, are presented: first, a Sigfox-based temperature-humidity index (THI) sensor to monitor the impact of heat stress in livestock, then a LoRaWAN version of an estrus detection collar for dairy farms, and finally a NB-IoT low-power A-GPS geolocation device for animals. Detailed power consumption measurements are presented and compared to highlight the benefits of each low-power wide-area network technology for the industry. The measured energy to transmit a single 10Byte payload packet was 90, 20, and 90 mJ for Sigfox, LoRa, and NB-IoT, respectively. With an adequate power management strategy, the nodes could operate up to 10 years in the case of the THI and estrus detector, and >1 yr in the case of the GPS tracker, powered by a single 1900 mA\u0000<inline-formula> <tex-math>$cdot mathrm {h}~mathrm {LiSOCl}_{2}$ </tex-math></inline-formula>\u0000 battery.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 3","pages":"283-286"},"PeriodicalIF":1.7,"publicationDate":"2024-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140829762","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Improving Netlist Transformation-Based Approximate Logic Synthesis Through Resynthesis 通过重合成改进基于网表转换的近似逻辑合成
IF 1.7 4区 计算机科学
IEEE Embedded Systems Letters Pub Date : 2024-04-18 DOI: 10.1109/LES.2024.3391220
Roger Morales-Monge;Jorge Castro-Godínez;Guilherme Paim
{"title":"Improving Netlist Transformation-Based Approximate Logic Synthesis Through Resynthesis","authors":"Roger Morales-Monge;Jorge Castro-Godínez;Guilherme Paim","doi":"10.1109/LES.2024.3391220","DOIUrl":"10.1109/LES.2024.3391220","url":null,"abstract":"To address the challenges of efficient hardware design for error-tolerant applications, several techniques of applied approximate computing have been proposed. Pruning algorithms aim to approximate circuits with reduced design requirements at the cost of an acceptable degradation of their quality of result. In this letter, we present the effects of resynthesis, an iterative application of logic synthesis along with pruning algorithms, into a state-of-the-art approximate design flow, AxLS. Resynthesis strategy improves the approximation, achieving up to 70% area-power savings for the same error in the output, and reducing the number of iterations, and hence the time required to explore the design space in up to \u0000<inline-formula> <tex-math>$30times $ </tex-math></inline-formula>\u0000, to obtain an approximated design.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 3","pages":"279-282"},"PeriodicalIF":1.7,"publicationDate":"2024-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140630185","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Self-Tuning Model for Energy-Context Optimization in Perpetual Sensor Nodes Within IoT-Integrated Hydroponic Systems 物联网集成水栽系统中永久传感器节点的能量情境优化自调整模型
IF 1.7 4区 计算机科学
IEEE Embedded Systems Letters Pub Date : 2024-04-10 DOI: 10.1109/LES.2024.3387310
A. Hernández-Benítez;J. Vázquez-Castillo;Johan J. Estrada-López;G. Becerra-Nunez;N. Cólin-García;A. Castillo-Atoche
{"title":"Self-Tuning Model for Energy-Context Optimization in Perpetual Sensor Nodes Within IoT-Integrated Hydroponic Systems","authors":"A. Hernández-Benítez;J. Vázquez-Castillo;Johan J. Estrada-López;G. Becerra-Nunez;N. Cólin-García;A. Castillo-Atoche","doi":"10.1109/LES.2024.3387310","DOIUrl":"10.1109/LES.2024.3387310","url":null,"abstract":"Hydroponic farming is a promising alternative to soil-based farming. However, it requires a precise control of the growth environment, which is hard to achieve with energy-constrained embedded systems. This letter presents an energy optimization technique for the continuous operation of energy harvesting-based hydroponics sensor nodes. The proposed technique is based on the self-tuning model, that dynamically adjust the duty cycle of the node, ensuring the autonomous operation of the Internet of Things system. The model can be programmed in a low-power microcontroller, allowing the decision-making process to reside entirely on the sensor node. Experimental results show that in the same time period, the self-tuning model allows \u0000<inline-formula> <tex-math>$3.5times $ </tex-math></inline-formula>\u0000 more data transmissions than a uniform 5-min duty cycle, while ensuring a minimum voltage level in the storage device. This balance allows the stored energy to be enough for continuous monitoring, providing a clean and cost-effective alternative to perpetually power the hydroponic system.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 3","pages":"267-270"},"PeriodicalIF":1.7,"publicationDate":"2024-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140569027","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Automated Parasite Control System Prototype Through Capsule Dosage Based on Image Processing 基于图像处理的胶囊剂量寄生虫自动控制系统原型
IF 1.7 4区 计算机科学
IEEE Embedded Systems Letters Pub Date : 2024-04-08 DOI: 10.1109/LES.2024.3386336
Ezequiel Carbajo;Lucas Leiva;Juan Toloza;Martín Vázquez;Silvina Fernández;Federica Sagües;Milagros Junco;Inés Guerrero;Sara Zegbi;Carlos Saumell
{"title":"Automated Parasite Control System Prototype Through Capsule Dosage Based on Image Processing","authors":"Ezequiel Carbajo;Lucas Leiva;Juan Toloza;Martín Vázquez;Silvina Fernández;Federica Sagües;Milagros Junco;Inés Guerrero;Sara Zegbi;Carlos Saumell","doi":"10.1109/LES.2024.3386336","DOIUrl":"10.1109/LES.2024.3386336","url":null,"abstract":"Digitalization and automation in the agricultural sector enable the enhancement of production processes, leading to increased yields. Specifically, the medications administration or complementary treatments in animals often prove to be a demanding task for human operators. This letter introduces an embedded system prototype that facilitates monitoring the level of capsules coverage in troughs through image processing. The suggested system enables an innovative antiparasitic treatment using biological control agents. The prototype utilizes a Raspberry Pi 3B as the platform to execute the developed image processing algorithm. The obtained results successfully demonstrate the algorithm’s accurate functionality estimating capsules coverage within the troughs.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 3","pages":"303-306"},"PeriodicalIF":1.7,"publicationDate":"2024-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140569348","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
FPGA-Based Digital Taylor–Fourier Transform 基于 FPGA 的数字泰勒-傅里叶变换
IF 1.7 4区 计算机科学
IEEE Embedded Systems Letters Pub Date : 2024-04-03 DOI: 10.1109/LES.2024.3384843
Gerardo Avalos-Almazan;Sarahi Aguayo-Tapia;Jose De Jesus Rangel-Magdaleno;Victor Aviña-Corral
{"title":"FPGA-Based Digital Taylor–Fourier Transform","authors":"Gerardo Avalos-Almazan;Sarahi Aguayo-Tapia;Jose De Jesus Rangel-Magdaleno;Victor Aviña-Corral","doi":"10.1109/LES.2024.3384843","DOIUrl":"10.1109/LES.2024.3384843","url":null,"abstract":"This research centers on the application of the discrete-time Taylor–Fourier transform (DTTFT) algorithmic implementation for phasor estimation on a field-programmable gate array board. The system employs a finite impulse response structure of a digital Taylor–Fourier filter to extract amplitude and phase information. The hardware description utilizes a multiply accumulator architecture with only forty embedded 9-bit multiplier elements, achieving an 18-bit input–output resolution. Performance assessment involves signal analysis through FPGA-in-the-loop simulation in MATLAB/Simulink. Findings demonstrate that the DTTFT-based phasor estimator can be effectively characterized using VHDL code and implemented on an Intel D2-115 board.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 3","pages":"299-302"},"PeriodicalIF":1.7,"publicationDate":"2024-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140569651","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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