On the Retiming for Register Minimization by Means of Breadth Coefficients Matrix

This letter is focused in the retiming technique for register minimization. This technique was presented as a minimum-cost linear problem, where the use of a fanout gadget was proposed to the model nodes (the functional blocks) in a digital circuit with multiple output edges to obtain a retiming solution $r(V)$ with integer values. The goal of this technique is to minimize the function ${\mathrm { COST}}^{\prime } =\sum _{e} \beta (e)\omega _{r} (e)$ subject to feasibility and clock period constraints. The determination of the breadth coefficients $\beta (e)$ could be cumbersome for large digital circuits, as there is no suitable method in the literature. Based on some concepts from graph theory and linear algebra, an algorithm for computing the breadth coefficients is proposed. An example is presented in order to illustrate the performance of the proposed algorithm as calculations for the breadth coefficients are effortless determined.