Reliable Methodology to FPGA Design Verification and Noise Analysis for Digital Lock-In Amplifiers

IF 1.7 4区计算机科学 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Embedded Systems Letters Pub Date : 2024-06-18 DOI:10.1109/LES.2024.3415651

Jose Alejandro Galaviz-Aguilar;Cesar Vargas-Rosales;Francisco Falcone

{"title":"Reliable Methodology to FPGA Design Verification and Noise Analysis for Digital Lock-In Amplifiers","authors":"Jose Alejandro Galaviz-Aguilar;Cesar Vargas-Rosales;Francisco Falcone","doi":"10.1109/LES.2024.3415651","DOIUrl":null,"url":null,"abstract":"The lock-in amplifier (LIA) instruments are designed to provide signal conditioning for precision measurement systems to extract signals from extremely noisy environments. The digital LIAs design often requires a verification process to ensure hardware performance. Thus, hardware description language (HDL) with functional verification strategies offers a powerful tool to provide an field-programmable gate array (FPGA) integrated solution. In this letter, we propose a methodology of design and verification of all-digital LIA and an additive white Gaussian noise (AWGN) module able to measure extremely lower levels of signal-to-noise ratio (SNR) of \n<inline-formula> <tex-math>$\\approx $ </tex-math></inline-formula>\n \n<inline-formula> <tex-math>${10}^{-{15}}$ </tex-math></inline-formula>\n or down to −37 dB while a wide reserve of spurious-free dynamic range (SFDR) up to 90 dB on FPGA is ensured. To this end, the designed and implemented FPGA framework for quick, accurate, and comprehensive characterization of a given digital LIA is used to leverage the capabilities of the design under controllable AWGN noise patterns stimulus.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 3","pages":"307-310"},"PeriodicalIF":1.7000,"publicationDate":"2024-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Embedded Systems Letters","FirstCategoryId":"94","ListUrlMain":"https://ieeexplore.ieee.org/document/10560037/","RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}

引用次数: 0

Abstract

The lock-in amplifier (LIA) instruments are designed to provide signal conditioning for precision measurement systems to extract signals from extremely noisy environments. The digital LIAs design often requires a verification process to ensure hardware performance. Thus, hardware description language (HDL) with functional verification strategies offers a powerful tool to provide an field-programmable gate array (FPGA) integrated solution. In this letter, we propose a methodology of design and verification of all-digital LIA and an additive white Gaussian noise (AWGN) module able to measure extremely lower levels of signal-to-noise ratio (SNR) of

$\approx $

${10}^{-{15}}$

or down to −37 dB while a wide reserve of spurious-free dynamic range (SFDR) up to 90 dB on FPGA is ensured. To this end, the designed and implemented FPGA framework for quick, accurate, and comprehensive characterization of a given digital LIA is used to leverage the capabilities of the design under controllable AWGN noise patterns stimulus.

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数字锁相放大器 FPGA 设计验证和噪声分析的可靠方法

锁相放大器（LIA）仪器的设计目的是为精密测量系统提供信号调节，以便从极度嘈杂的环境中提取信号。数字 LIA 设计通常需要验证过程，以确保硬件性能。因此，具有功能验证策略的硬件描述语言（HDL）为提供现场可编程门阵列（FPGA）集成解决方案提供了强有力的工具。在这封信中，我们提出了一种全数字 LIA 和加性白高斯噪声（AWGN）模块的设计和验证方法，该模块能够测量 ${10}^{-{15}}$ 或低至 -37 dB 的极低水平信噪比（SNR），同时确保 FPGA 具有高达 90 dB 的宽储备无杂散动态范围（SFDR）。为此，设计并实现了 FPGA 框架，用于快速、准确、全面地鉴定给定的数字 LIA，以充分利用设计在可控 AWGN 噪声模式刺激下的能力。

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来源期刊

IEEE Embedded Systems Letters Engineering-Control and Systems Engineering

CiteScore

3.30

自引率

0.00%

发文量

期刊介绍： The IEEE Embedded Systems Letters (ESL), provides a forum for rapid dissemination of latest technical advances in embedded systems and related areas in embedded software. The emphasis is on models, methods, and tools that ensure secure, correct, efficient and robust design of embedded systems and their applications.