基于 PCIe 的小数据包 DMA 传输的软硬件协同优化

IF 1.7 4区 计算机科学 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Xiaotian Gu;Lisong Shao;Ningfeng Bai;Guosheng Zhang;Xinyi Zhang
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引用次数: 0

摘要

本文章由计算机程序翻译,如有差异,请以英文原文为准。
A Co-Optimization of Software and Hardware for PCIe-Based Small Packet DMA Transfer
To meet the development needs of high-performance networks, the efficiency of PCIe DMA with small packet transmissions emerges as a critical performance bottleneck. For the purpose improving DMA transfer for small packets over PCIe, we focus on the symbiotic co-optimization of software and hardware. By enhancing the software driver with descriptor prefetching, harnessing the outstanding capability at the hardware level, and using multicore for parallel processing, the system’s bandwidth has been significantly improved, particularly for the small packets transfers. Postoptimization, we test the DMA read and write bandwidth and utilization rate performance on VC709 FPGA. In a randomized test scenario, the average DMA read bandwidth is approximately 5.3 GB/s, representing a 123% improvement compared to the unoptimized system bandwidth. The average DMA write bandwidth is approximately 5.8 GB/s, representing a 136% improvement compared to the unoptimized system bandwidth. Additionally, in the randomized test scenario, the average read and write latencies improved by 15.12% and 23.96%, respectively.
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来源期刊
IEEE Embedded Systems Letters
IEEE Embedded Systems Letters Engineering-Control and Systems Engineering
CiteScore
3.30
自引率
0.00%
发文量
65
期刊介绍: The IEEE Embedded Systems Letters (ESL), provides a forum for rapid dissemination of latest technical advances in embedded systems and related areas in embedded software. The emphasis is on models, methods, and tools that ensure secure, correct, efficient and robust design of embedded systems and their applications.
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