PAC 码快速列表解码器的软件实现

IF 1.7 4区计算机科学 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Embedded Systems Letters Pub Date : 2024-06-20 DOI:10.1109/LES.2024.3417413

Hang Yin;Jingxin Dai;Yansong Lv;Yuhuan Wang;Rui Lv

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Software Implementation of Fast List Decoder for PAC Codes

In this letter, a novel high throughput software polarization-adjusted convolutional (PAC) decoder based on the four-node fast list (FFL) decoding algorithm is proposed. To improve the parallel processing capabilities of the proposed decoder, we effectively parallel map the FFL decoding algorithm to processors by using the single-instruction-multiple-data (SIMD) instruction set to decode multiple frames of data in parallel. Moreover, the proposed decoder has sufficient generality to be implemented on X86 and ARM processors (NEON, SSE, and AVX256 instruction sets). Experimentations show that the proposed software PAC decoder can achieve 26.256 Mb/s.

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来源期刊

IEEE Embedded Systems Letters Engineering-Control and Systems Engineering

CiteScore

3.30

自引率

0.00%

发文量

期刊介绍： The IEEE Embedded Systems Letters (ESL), provides a forum for rapid dissemination of latest technical advances in embedded systems and related areas in embedded software. The emphasis is on models, methods, and tools that ensure secure, correct, efficient and robust design of embedded systems and their applications.