IEEE Embedded Systems Letters最新文献_第4页

Hiding in Plain Sight: Reframing Hardware Trojan Benchmarking as a Hide&Seek Modification 隐藏在显而易见的地方：重新构建硬件木马基准测试作为一个捉迷藏的修改

IF 1.7 4区计算机科学

IEEE Embedded Systems Letters Pub Date : 2024-12-05 DOI: 10.1109/LES.2024.3443155

Amin Sarihi;Ahmad Patooghy;Peter Jamieson;Abdel-Hameed A. Badawy

{"title":"Hiding in Plain Sight: Reframing Hardware Trojan Benchmarking as a Hide&Seek Modification","authors":"Amin Sarihi;Ahmad Patooghy;Peter Jamieson;Abdel-Hameed A. Badawy","doi":"10.1109/LES.2024.3443155","DOIUrl":"https://doi.org/10.1109/LES.2024.3443155","url":null,"abstract":"This letter focuses on advancing security research in the hardware design space by formally defining the realistic problem of hardware Trojan (HT) detection. The goal is to model HT detection more closely to the real world, i.e., describing the problem as “The Seeker’s Dilemma” where a detecting agent is unaware of whether circuits are infected by HTs or not. Using this theoretical problem formulation, we create a benchmark that consists of a mixture of HT-free and HT-infected restructured circuits while preserving their original functionalities. The restructured circuits are randomly infected by HTs, causing a situation where the defender is uncertain if a circuit is infected or not. We believe that our innovative benchmark and methodology of creating benchmarks will help the community judge the detection quality of different methods by comparing their success rates in circuit classification. We use our developed benchmark to evaluate three state-of-the-art HT detection tools to show baseline results for this approach. We use principal component analysis to assess the strength of our benchmark, where we observe that some restructured HT-infected circuits are mapped closely to HT-free circuits, leading to significant label misclassification by detectors.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 4","pages":"361-364"},"PeriodicalIF":1.7,"publicationDate":"2024-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142789108","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

ViTSen: Bridging Vision Transformers and Edge Computing With Advanced In/Near-Sensor Processing ViTSen：桥接视觉变压器和边缘计算与先进的内/近传感器处理

IF 1.7 4区计算机科学

IEEE Embedded Systems Letters Pub Date : 2024-12-05 DOI: 10.1109/LES.2024.3449240

Sepehr Tabrizchi;Brendan C. Reidy;Deniz Najafi;Shaahin Angizi;Ramtin Zand;Arman Roohi

引用次数: 0

SpiKernel: A Kernel Size Exploration Methodology for Improving Accuracy of the Embedded Spiking Neural Network Systems SpiKernel：一种用于提高嵌入式尖峰神经网络系统精度的核尺寸探索方法

IF 1.7 4区计算机科学

IEEE Embedded Systems Letters Pub Date : 2024-12-02 DOI: 10.1109/LES.2024.3510197

Rachmad Vidya Wicaksana Putra;Muhammad Shafique

{"title":"SpiKernel: A Kernel Size Exploration Methodology for Improving Accuracy of the Embedded Spiking Neural Network Systems","authors":"Rachmad Vidya Wicaksana Putra;Muhammad Shafique","doi":"10.1109/LES.2024.3510197","DOIUrl":"https://doi.org/10.1109/LES.2024.3510197","url":null,"abstract":"Spiking neural networks (SNNs) can offer ultralow power/energy consumption for machine learning-based application tasks due to their sparse spike-based operations. Currently, most of the SNN architectures need a significantly larger model size to achieve higher accuracy, which is not suitable for resource-constrained embedded applications. Therefore, developing SNNs that can achieve high accuracy with acceptable memory footprint is highly needed. Toward this, we propose SpiKernel, a novel methodology that improves the accuracy of SNNs through kernel size exploration. Its key steps include: 1) investigating the impact of different kernel sizes on the accuracy; 2) devising new sets of kernel sizes; 3) generating SNN architectures using neural architecture search based on the selected kernel sizes; and 4) analyzing the accuracy-memory tradeoffs for SNN model selection. The experimental results show that our SpiKernel achieves higher accuracy than state-of-the-art works (i.e., 93.24% for CIFAR10, 70.84% for CIFAR100, and 62% for TinyImageNet) with less than 10 M parameters and up to <inline-formula> <tex-math>$4.8times $ </tex-math></inline-formula> speed-up of searching time, thereby making it suitable for embedded applications.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"17 3","pages":"151-155"},"PeriodicalIF":1.7,"publicationDate":"2024-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144272966","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

High-Efficient Approximate Subtractors for Change Detection Applications 变化检测应用的高效近似减法

IF 1.7 4区计算机科学

IEEE Embedded Systems Letters Pub Date : 2024-12-02 DOI: 10.1109/LES.2024.3510416

Fatemeh Pooladi;Farshad Pesaran;Nabiollah Shiri

引用次数: 0

TENDRA: Targeted Endurance Attack on STT-RAM LLC 对STT-RAM有限责任公司的目标持久攻击

IF 1.7 4区计算机科学

IEEE Embedded Systems Letters Pub Date : 2024-11-19 DOI: 10.1109/LES.2024.3502297

Prabuddha Sinha;Mangena Likhit Sai;Shirshendu Das;Venkata Kalyan Tavva

引用次数: 0

FPGA Implementation of an Image Classifier Using Pipelined FFT Architecture 基于流水线FFT架构的图像分类器的FPGA实现

IF 1.7 4区计算机科学

IEEE Embedded Systems Letters Pub Date : 2024-11-18 DOI: 10.1109/LES.2024.3500020

Shafiqul Hai;Tella Rajashekhar Reddy

{"title":"FPGA Implementation of an Image Classifier Using Pipelined FFT Architecture","authors":"Shafiqul Hai;Tella Rajashekhar Reddy","doi":"10.1109/LES.2024.3500020","DOIUrl":"https://doi.org/10.1109/LES.2024.3500020","url":null,"abstract":"Deep neural network (DNN) belongs to an important class of machine learning algorithms generally used to classify digital data in the form of image and speech recognition. The computational complexity of a DNN-based image classifier is higher than traditional fully connected (FC) feed-forward NNs. Therefore, dedicated cloud servers and graphical processor units (GPUs) are utilized to achieve high-speed and large-capacity computation tasks in machine vision systems. However, a growing demand exists for real-time processing of complex machine-learning tasks on embedded systems. As FC layers consume the highest fraction of computational power and memory footprint, innovating novel power-efficient and low-footprint NN architecture for embedded systems is crucial. In this letter, a pipelined and parallel fast Fourier transform (FFT)-based FC-DNN architecture is implemented on Stratix-10 FPGA using VHDL. The footprint of the DNN is further reduced using a folded FFT network. The proposed algorithm is tested using two benchmark training set examples, the MNIST database of handwritten digits and the CIFAR-10 database. In both cases, we achieve <inline-formula> <tex-math>${gt }~90$ </tex-math></inline-formula>% accuracy, while the power consumption of the 2-parallel folded FFT-based network is around 45% less than the traditional series FFT-based architectures.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"17 3","pages":"188-191"},"PeriodicalIF":1.7,"publicationDate":"2024-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144272960","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

TLP Balancer: Predictive Thread Allocation for Multitenant Inference in Embedded GPUs TLP平衡器：嵌入式gpu中多租户推理的预测线程分配

IF 1.7 4区计算机科学

IEEE Embedded Systems Letters Pub Date : 2024-11-14 DOI: 10.1109/LES.2024.3497587

Minseong Gil;Jaebeom Jeon;Junsu Kim;Sangun Choi;Gunjae Koo;Myung Kuk Yoon;Yunho Oh

引用次数: 0

Lustre, Fast First, and Fresh 光泽，快第一，新鲜

IF 1.7 4区计算机科学

IEEE Embedded Systems Letters Pub Date : 2024-11-14 DOI: 10.1109/LES.2024.3498932

Timothy Bourke;Marc Pouzet

引用次数: 0

Towards Energy-Accuracy Scalable Multimodal Cognitive Systems 面向能量-精度可扩展多模态认知系统

IF 1.7 4区计算机科学

IEEE Embedded Systems Letters Pub Date : 2024-11-13 DOI: 10.1109/LES.2024.3497935

Soumendu Kumar Ghosh;Arghadip Das;Arnab Raha;Vijay Raghunathan

{"title":"Towards Energy-Accuracy Scalable Multimodal Cognitive Systems","authors":"Soumendu Kumar Ghosh;Arghadip Das;Arnab Raha;Vijay Raghunathan","doi":"10.1109/LES.2024.3497935","DOIUrl":"https://doi.org/10.1109/LES.2024.3497935","url":null,"abstract":"Transformer-powered multimodal artificial intelligence (MMAI) holds great promise for developing cognitive systems that can analyze and interpret data from various sensory modalities simultaneously. However, deploying MMAI on resource-constrained “edge” platforms poses significant challenges due to the intensive compute and memory requirements of transformer models, communication bandwidth limitations, real-time processing needs, and the intricacies of multimodal data fusion. To overcome these challenges, we introduce collaborative multimodal inference, leveraging the strengths of MMAI, edge computing, and cloud resources. Our solution introduces modality-aware accuracy-efficiency (AE) knobs, extending beyond multimodal sensors to individual subsystems within the edge system. We explore intersubsystem and intermodal interactions, investigating system-level AE tradeoffs in the presence of synergistic optimizations. Building on these insights, we present <monospace>SysteMMX</monospace>, the first AE scalable cognitive system for efficient multimodal inference at the edge. In this letter, we present an in-depth case study centered around a multimodal system employing RGB and depth sensors for image segmentation. Our system, <monospace>SysteMMX</monospace>, demonstrates significant energy savings—<inline-formula> <tex-math>${1.8 times }$ </tex-math></inline-formula> on the edge device and <inline-formula> <tex-math>${1.7times }$ </tex-math></inline-formula> on the edge server—with an imperceptible application-level accuracy loss of less than 0.01%. Furthermore, <monospace>SysteMMX</monospace> outperforms single-modality optimizations, achieving <inline-formula> <tex-math>${1.2times }$ </tex-math></inline-formula> and <inline-formula> <tex-math>${1.8times }$ </tex-math></inline-formula> more energy efficiency on the edge compared to RGB-only and Depth-only approaches, respectively, for similar levels of accuracy loss.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"17 3","pages":"156-159"},"PeriodicalIF":1.7,"publicationDate":"2024-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144272958","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Investigation of Security Vulnerabilities in NVM-Based Persistent TinyML Hardware 基于nvm的持久性TinyML硬件安全漏洞研究

IF 1.7 4区计算机科学

IEEE Embedded Systems Letters Pub Date : 2024-11-12 DOI: 10.1109/LES.2024.3496508

Bhanprakash Goswami;Chithambara J. Moorthii;Harshit Bansal;Ayan Sajwan;Manan Suri

引用次数: 0