Zhuowen Zou;Yang Ni;SungHeon Jeong;Satish Ravindran;Binbin Shi;Phil Chen;Mohsen Imani
{"title":"DynHD: Hyperdimensional Computing Approach for Efficient Radar Spectrum Classification","authors":"Zhuowen Zou;Yang Ni;SungHeon Jeong;Satish Ravindran;Binbin Shi;Phil Chen;Mohsen Imani","doi":"10.1109/LES.2024.3485638","DOIUrl":"https://doi.org/10.1109/LES.2024.3485638","url":null,"abstract":"Radar technology plays a critical role in target detection, classification, and tracking. However, the computational demands of training deep neural networks (DNNs) on radar signals can be overwhelming, posing challenges for edge devices with limited energy and computing resources. In this article, we propose leveraging hyperdimensional computing (HDC), a brain-inspired computing paradigm, as an efficient alternative. HDC utilizes high-dimensional vectors for information representation and processing, offering robustness and energy efficiency. We propose a novel HDC classification algorithm named DynHD, with a dynamic HDC encoder that adapts to more challenging radar spectrum recognition tasks. We designed this mechanism to provide great flexibility to the HDC encoder that is otherwise fixed. Our evaluations demonstrate that HDC-based approaches achieve comparable accuracy to DNN-based methods with lower-computational complexity, making them suitable for resource-constrained devices. We achieve significant improvements in latency during training and inference phases, enabling efficient processing of radar signals on edge devices.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"17 2","pages":"95-98"},"PeriodicalIF":1.7,"publicationDate":"2024-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10734137","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143845510","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Yuchen Nie;Sheng Zhong;Nailiang Kuang;Yuting Ji;Hangzai Luo
{"title":"An Optimized Structure for Data Alignment Logic in Parallel CRC Computing Circuits","authors":"Yuchen Nie;Sheng Zhong;Nailiang Kuang;Yuting Ji;Hangzai Luo","doi":"10.1109/LES.2024.3485632","DOIUrl":"https://doi.org/10.1109/LES.2024.3485632","url":null,"abstract":"In bit-level parallel cyclic redundancy check (CRC) computing circuits, it is possible that the input data length may not be evenly divisible by the parallel bit width. Consequently, the incorporation of alignment logic into the circuit is necessary to discard the invalid data. A comprehensive analysis of 256-bits parallel circuits reveals that the data alignment structure introduces an additional delay of 46% to 53.8%. We proposed a prealignment structure as a means of optimizing the data alignment logic. This structure separates the data alignment logic from the loopback structure generated by the parallel computing logic, allowing for pipelining between the data alignment logic and the parallel computing logic. On-board tests on field-programmable gate arrays (FPGAs) show that circuits with a prealignment structure have an increase in maximum clock frequency of about 95% to 175% and a reduction in average energy consumption for computation of about 40.6% to 55% compared to circuits using a shift-alignment structure.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"17 2","pages":"91-94"},"PeriodicalIF":1.7,"publicationDate":"2024-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143845580","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"PRIOT: Pruning-Based Integer-Only Transfer Learning for Embedded Systems","authors":"Honoka Anada;Sefutsu Ryu;Masayuki Usui;Tatsuya Kaneko;Shinya Takamaeda-Yamazaki","doi":"10.1109/LES.2024.3485003","DOIUrl":"https://doi.org/10.1109/LES.2024.3485003","url":null,"abstract":"On-device transfer learning is crucial for adapting a common backbone model to the unique environment of each edge device. Tiny microcontrollers, such as the Raspberry Pi Pico, are key targets for on-device learning but often lack floating-point units, necessitating integer-only training. Dynamic computation of quantization scale factors, which is adopted in former studies, incurs high computational costs. Therefore, this letter focuses on integer-only training with static-scale factors, which is challenging with existing training methods. We propose a new training method named PRIOT, which optimizes the network by pruning selected edges rather than updating weights, allowing effective training with static-scale factors. The pruning pattern is determined by the edge-popup algorithm, which trains a parameter named score assigned to each edge instead of the original parameters and prunes the edges with low scores before inference. Additionally, we introduce a memory-efficient variant, PRIOT-S, which only assigns scores to a small fraction of edges. We implement PRIOT and PRIOT-S on the Raspberry Pi Pico and evaluate their accuracy and computational costs using a tiny CNN model on the rotated MNIST dataset and the VGG11 model on the rotated CIFAR-10 dataset. Our results demonstrate that PRIOT improves accuracy by 8.08–33.75 percentage points over existing methods, while PRIOT-S reduces memory footprint with minimal accuracy loss.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"17 2","pages":"87-90"},"PeriodicalIF":1.7,"publicationDate":"2024-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143845335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Novel One-Versus-All Approach for Multiclass Classification in TinyML Systems","authors":"Tobiasz Puślecki;Krzysztof Walkowiak","doi":"10.1109/LES.2024.3482002","DOIUrl":"https://doi.org/10.1109/LES.2024.3482002","url":null,"abstract":"The recent progress in TinyML technologies triggers the need to address the challenge of balancing inference time and recognition quality. TinyML systems are defined by specific constraints in computation, memory and energy. These constraints emphasize the need for specialized optimization techniques when implementing machine learning (ML) applications on such platforms. While deep neural networks are popular in TinyML systems, exploring simple classifiers is also worthwhile. In this work, we consider a modification of the one-versus-all (OVA) approach in a multiclass task of computer vision in TinyML systems. This modification, named thresholded OVA (TOVA), enables control over classification accuracy, influencing both latency and energy consumption per inference. By testing various combinations of hyperparameters, we simulate the performance of a real device using metrics specific to TinyML systems. The results show that the proposed method significantly saves energy and speeds up computation, at the cost of slightly lower-overall accuracy of the TinyML system.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"17 2","pages":"71-74"},"PeriodicalIF":1.7,"publicationDate":"2024-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143845409","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Analysis of S-Box Hardware Resources to Improve AES Intrinsic Security Against Power Attacks","authors":"Thockchom Birjit Singha;Roy Paily Palathinkal;Shaik Rafi Ahamed","doi":"10.1109/LES.2024.3478070","DOIUrl":"https://doi.org/10.1109/LES.2024.3478070","url":null,"abstract":"Side-channel attacks (SCAs) have rendered Internet of Things (IoT)-based devices unsafe despite employing Advanced Encryption Standard (AES) as the cryptographic algorithm. Additional circuitry, called countermeasures, is used to protect AES against the attacks at the cost of huge area and power overheads. The attacks are performed on SubBytes round operation of AES, which comprises of 16 S-boxes. This letter makes a novel attempt to boost the intrinsic security of an unprotected AES by analyzing four smallest composite field arithmetic (CFA)-based S-boxes available in literature, Circuit Minimization Team (CMT), Canright, Maximov, and Masoleh with lookup table (LUT)-based S-box as a reference. This letter proposes an AES design which is unprotected but with enhanced security. The designer can aim higher security by adding smaller countermeasure protective schemes before incorporating into IoT devices. A novel 3-D hardware analysis, namely, hardware resources, hardware complexity/linearity, and hardware security, is performed which demonstrates that lesser gate equivalent (GE) and linear gates of Masoleh S-box offer the highest security. Upon evaluation on Side-Channel Attack Standard Evaluation Board (SASEBO), all the hardware security metrics favored Masoleh S-box, depicting nearly \u0000<inline-formula> <tex-math>$94 times $ </tex-math></inline-formula>\u0000 gain in security and 80% reduction in area with respect to other unprotected designs.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 4","pages":"525-528"},"PeriodicalIF":1.7,"publicationDate":"2024-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142777725","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Simplified Oblique Decision Tree Accelerator","authors":"Rituparna Choudhury;Shaik Rafi Ahamed;Prithwijit Guha","doi":"10.1109/LES.2024.3475397","DOIUrl":"https://doi.org/10.1109/LES.2024.3475397","url":null,"abstract":"In recent years, hardware platforms like field programmable gate arrays (FPGAs) and application specific integrated circuits (ASICs) are highly preferred for implementing machine learning algorithms in low-power or high-speed applications. This letter proposes a simplified oblique node decision tree algorithm. The classification is implemented on FPGA and ASIC for activity recognition and Parkinson’s tremor detection. A mode number is used to choose the application mode. To provide better classification performance, efficient multiplier-less architectures have been used for power efficiency. This design operates at a maximum frequency of 167 MHz and has the lowest latency as compared to the existing hardware. It is also found to have very low resource consumption as compared to other existing high-speed architectures.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"17 2","pages":"79-82"},"PeriodicalIF":1.7,"publicationDate":"2024-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143845509","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Implementation of Polyphase Digital Down Converter Using Optimized LMS Algorithm for WCDMA Application","authors":"Debarshi Datta;Mrinal Kanti Naskar","doi":"10.1109/LES.2024.3473539","DOIUrl":"https://doi.org/10.1109/LES.2024.3473539","url":null,"abstract":"This letter presents the implementation of a polyphase digital down converter (DDC) that employs a least mean square (LMS) algorithm associated with particle swarm optimization (PSO) for the wideband code division multiple access (WCDMA) application. The PSO-based LMS algorithm suppresses the noise signal, enabling a significant improvement in the spurious-free dynamic range (SFDR), which is 130 dB. The complex multiplication is realized by the canonical impel-mentation to reduce the number of multipliers. The suggested polyphase DDC architecture is successfully implemented in the field-programmable gate array device (FPGA) Kintex-7 platform. To achieve high accuracy, the proposed design is implemented with an efficient user-defined floating-point representation data type. Synthesis results suggested that the design consumes less area and power compared to the most recent structure.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 4","pages":"533-536"},"PeriodicalIF":1.7,"publicationDate":"2024-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142777800","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Abdollah Masoud Darya;Sohaib Majzoub;Ali A. El-Moursy;Mohamed Wed Eladham;Khalid Javeed;Ahmed S. Elwakil
{"title":"Using Intermittent Chaotic Clocks to Secure Cryptographic Chips","authors":"Abdollah Masoud Darya;Sohaib Majzoub;Ali A. El-Moursy;Mohamed Wed Eladham;Khalid Javeed;Ahmed S. Elwakil","doi":"10.1109/LES.2024.3472709","DOIUrl":"https://doi.org/10.1109/LES.2024.3472709","url":null,"abstract":"This letter proposes using intermittent chaotic clocks, generated from chaotic maps, to drive cryptographic chips running the advanced encryption standard as a countermeasure against correlation power analysis (CPA) attacks. Five different chaotic maps, namely, the logistic map, the Bernoulli shift map, the Henon map, the tent map, and the Ikeda map, are used in this letter to generate chaotic clocks. The performance of these chaotic clocks is evaluated in terms of timing overhead and the resilience of the driven chip against CPA attacks. All proposed chaotic clocking schemes successfully protect the driven chip against attacks, with the clocks produced by the optimized Ikeda, Henon, and logistic maps achieving the lowest-timing overhead. These optimized maps, due to their intermittent chaotic behavior, exhibit lower-timing overhead compared to previous work. Notably, the chaotic clock generated by the optimized Ikeda map approaches the theoretical limit of timing overhead, i.e., half the execution time of a reference periodic clock.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 4","pages":"529-532"},"PeriodicalIF":1.7,"publicationDate":"2024-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142777823","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"TinyML-Based Intrusion Detection System for In-Vehicle Network Using Convolutional Neural Network on Embedded Devices","authors":"Hyungchul Im;Seongsoo Lee","doi":"10.1109/LES.2024.3475470","DOIUrl":"https://doi.org/10.1109/LES.2024.3475470","url":null,"abstract":"This letter proposes a novel model for effectively detecting malicious messages in controller area network (CAN) communication, which is widely used in automotive networks. Because in-vehicle networks operate in resource-constrained environments, an intrusion detection system (IDS) must simultaneously provide a low computational load and excellent detection performance. However, existing models are unsuitable for deployment on low-power embedded devices owing to their high computational requirements. This letter presents a low-complexity convolutional neural network (CNN)-based IDS for deployment on embedded edge devices. The proposed model applies CNN operations separately to the CAN ID sequence and the data field of the CAN frame to extract features and concatenate them for feature fusion. Experimental results demonstrate that this approach requires considerably less computational load and provides superior detection performance. Furthermore, the proposed model is deployed on a resource-constrained nRF52840 microcontroller using TensorFlow Lite for Microcontrollers with 20.44-kB flash memory and 26.44-kB RAM without quantization.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"17 2","pages":"67-70"},"PeriodicalIF":1.7,"publicationDate":"2024-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143845336","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"MQTT-Based Adaptive Estimation Over Distributed Network Using Raspberry Pi Pico W","authors":"Prantaneel Debnath;Anshul Gusain;Parth Sharma;Pyari Mohan Pradhan","doi":"10.1109/LES.2024.3473017","DOIUrl":"https://doi.org/10.1109/LES.2024.3473017","url":null,"abstract":"As the demand for edge computing applications continues to rise, the need for efficient training of resource-constrained devices becomes paramount. This letter proposes message queuing telemetry transport (MQTT)-based implementation of distributed estimation strategies in the context of the Internet of Things (IoT), namely incremental, consensus, and diffusion strategies. The use of Raspberry Pi Pico W in the emulation environment is motivated by its advanced capability, while the MQTT data protocol is employed to address the constraints associated with conventional HTTP/HTTPs protocols. Synchronization in an IoT network is achieved by the integration of a novel methodology that entails the use of the wait-for-slowest (WFS) protocol and the MQTT protocol. Furthermore, the development of a graphical user interface supported by the Django application allows for adjusting parameters in distributed strategies through the HTTP REST API, along with SQLite. The results acquired from hardware experiments exhibit a strong correlation between the mean-square performance achieved from simulation studies. The distributed estimation strategy is compared with state-of-the art centralized and noncooperation estimation strategies, demonstrating its superior performance. In addition, a study is conducted on the resilience of these IoT networks in the face of several network threats, such as node failure and model poisoning attacks. A theoretical analysis is provided to explain the relationship between the number of iterations and node failure.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 4","pages":"517-520"},"PeriodicalIF":1.7,"publicationDate":"2024-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142777798","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}