IEEE Embedded Systems Letters最新文献_第4页

A Provably Secure Scheme to Prevent Master Key Recovery by Fault Attack on AES Hardware 防止AES硬件故障攻击恢复主密钥的可证明安全方案

IF 1.7 4区计算机科学

IEEE Embedded Systems Letters Pub Date : 2024-10-03 DOI: 10.1109/LES.2024.3472673

Sneha Swaroopa;Sivappriya Manivannan;Rajat Subhra Chakraborty;Indrajit Chakrabarti

{"title":"A Provably Secure Scheme to Prevent Master Key Recovery by Fault Attack on AES Hardware","authors":"Sneha Swaroopa;Sivappriya Manivannan;Rajat Subhra Chakraborty;Indrajit Chakrabarti","doi":"10.1109/LES.2024.3472673","DOIUrl":"https://doi.org/10.1109/LES.2024.3472673","url":null,"abstract":"We explore a relatively lightweight scheme to prevent key recovery by fault attacks on the advanced encryption standard (AES) cipher. We employ a transformed key (derived from the original key through a nonlinear and possibly one-way mapping) for AES encryption hardware. The mapping combines processing using a pseudorandom bitstream generator (the keystream generator of the Grain-128a stream cipher), followed by a self-shrinking generator (SSG). We provide formal proof of security of the scheme, based on the assumed difficulty of inverting the output of the proposed key transformer. The design of the key transformer ensures that it is itself resistant to fault-attack. Our scheme requires a 96-bit secret initial value (IV), a one-time initial latency (approximately 256 clock cycles for a 128-bit key) of generating the transformed key, and a key transformation layer. However, the core AES hardware is left unchanged. We present hardware platform-based experimental results for an FPGA implementation, which incurs less hardware overhead than previously proposed fault attack prevention/detection schemes.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 4","pages":"521-524"},"PeriodicalIF":1.7,"publicationDate":"2024-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142777518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Scalable Dynamic Segmented Bus Interconnect for Neuromorphic Architectures 面向神经形态体系结构的可扩展动态分段总线互连

IF 1.7 4区计算机科学

IEEE Embedded Systems Letters Pub Date : 2024-09-23 DOI: 10.1109/LES.2024.3452551

Phu Khanh Huynh;Ilknur Mustafazade;Francky Catthoor;Nagarajan Kandasamy;Anup Das

{"title":"A Scalable Dynamic Segmented Bus Interconnect for Neuromorphic Architectures","authors":"Phu Khanh Huynh;Ilknur Mustafazade;Francky Catthoor;Nagarajan Kandasamy;Anup Das","doi":"10.1109/LES.2024.3452551","DOIUrl":"https://doi.org/10.1109/LES.2024.3452551","url":null,"abstract":"Large-scale neuromorphic architectures consist of computing tiles that communicate spikes using a shared interconnect. We propose ADIONA, a dynamic segmented bus interconnect to address design scalability while reducing energy and latency of spike traffic. ADIONA consists of parallel bus lanes arranged in a ladder-shaped structure that allows any tile to connect to another, offers multiple routing options for communication links, and provides a high level of customization for different mapping scenarios and use cases. Each lane in the ladder bus is partitioned into segments using lightweight bufferless switches. Based on compile-time communication information, these switches can be dynamically reconfigured at runtime to execute the target application. Our dynamic segmented bus interconnect substantially enhances hardware utilization, improves fault tolerance, and offers adaptability to execute different applications on a single hardware platform. We evaluate ADIONA using three synthetic and three realistic machine learning workloads on a cycle-accurate neuromorphic simulator. Our results show that ADIONA reduces energy consumption by \u0000<inline-formula> <tex-math>$2.1times $ </tex-math></inline-formula>\u0000, latency by \u0000<inline-formula> <tex-math>$40times $ </tex-math></inline-formula>\u0000, and interconnect area by \u0000<inline-formula> <tex-math>$2times $ </tex-math></inline-formula>\u0000, compared to a state-of-the-art interconnect for neuromorphic systems.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 4","pages":"505-508"},"PeriodicalIF":1.7,"publicationDate":"2024-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142777790","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An Embedded Module of Enhanced Turbo Product Code Algorithm 一种增强Turbo产品编码算法的嵌入式模块

IF 1.7 4区计算机科学

IEEE Embedded Systems Letters Pub Date : 2024-09-20 DOI: 10.1109/LES.2024.3464517

Jianjun Luo;Yifan Shen;Boming Huang;Michael Etzkorn;Hongqiang Chen;Cong Yu

引用次数: 0

Time-Sensitive Networking in Low Latency Cyber-Physical Systems 低延迟网络物理系统中的时间敏感型网络连接

IF 1.6 4区计算机科学

IEEE Embedded Systems Letters Pub Date : 2024-09-18 DOI: 10.1109/les.2024.3463545

Henrik Austad, Geir Mathisen

引用次数: 0

FedTinyWolf—A Memory Efficient Federated Embedded Learning Mechanism FedTinyWolf - 一种内存高效的联合嵌入式学习机制

IF 1.7 4区计算机科学

IEEE Embedded Systems Letters Pub Date : 2024-09-17 DOI: 10.1109/LES.2024.3462638

Subhrangshu Adhikary;Subhayu Dutta

引用次数: 0

SCALLER: Standard Cell Assembled and Local Layout Effect-Based Ring Oscillators SCALLER：基于标准单元组装和局部布局效应的环形振荡器

IF 1.7 4区计算机科学

IEEE Embedded Systems Letters Pub Date : 2024-09-12 DOI: 10.1109/LES.2024.3459730

Muayad J. Aljafar;Zain Ul Abideen;Adriaan Peetermans;Benedikt Gierlichs;Samuel Pagliarini

引用次数: 0

Comparing XML and JSON Characteristics as Formats for Data Serialization Within Ultralow Power Embedded Systems 比较 XML 和 JSON 作为超低功耗嵌入式系统数据序列化格式的特点

IF 1.7 4区计算机科学

IEEE Embedded Systems Letters Pub Date : 2024-08-28 DOI: 10.1109/LES.2024.3450576

James Gerrans;R. Simon Sherratt

{"title":"Comparing XML and JSON Characteristics as Formats for Data Serialization Within Ultralow Power Embedded Systems","authors":"James Gerrans;R. Simon Sherratt","doi":"10.1109/LES.2024.3450576","DOIUrl":"10.1109/LES.2024.3450576","url":null,"abstract":"Javascript object notation (JSON) and extensible markup language (XML) are two data serialization methods that have been compared over many applications, including client-server transmission, Internet communication, and large-scale data storage. Due to the smaller file size, JSON is faster for transmitting data. However, XML is better for sending complex data structures. This letter compares the two data formats in the context of an embedded system, considering factors, such as time, memory, and power to identify efficient characteristics of each method. Programs for each format were written, optimized, and compared for the same dataset. The JSON file was found to be 24.7% smaller than the XML file. This led to a shorter program run-time and less power being consumed when reading and processing the file. However, the program to deserialize the XML file took up 16.7% less flash memory than its JSON counterpart. Overall, JSON was found to be a better choice for systems when collecting large amounts of data, requiring high speed communication, or running for an extended period between battery charges. However, XML is proposed for systems that have limited flash memory.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 4","pages":"489-492"},"PeriodicalIF":1.7,"publicationDate":"2024-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142199416","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

IEEE Embedded Systems Letters Publication Information IEEE Embedded Systems Letters 出版信息

IF 1.7 4区计算机科学

IEEE Embedded Systems Letters Pub Date : 2024-08-28 DOI: 10.1109/LES.2024.3396921