TLP Balancer: Predictive Thread Allocation for Multitenant Inference in Embedded GPUs

IF 1.7 4区 计算机科学 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Minseong Gil;Jaebeom Jeon;Junsu Kim;Sangun Choi;Gunjae Koo;Myung Kuk Yoon;Yunho Oh
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引用次数: 0

Abstract

This letter introduces a novel software technique to optimize thread allocation for merged and fused kernels in multitenant inference systems on embedded graphics processing units (GPUs). Embedded systems equipped with GPUs face challenges in managing diverse deep learning workloads while adhering to quality-of-service (QoS) standards, primarily due to limited hardware resources and the varied nature of deep learning models. Prior work has relied on static thread allocation strategies, often leading to suboptimal hardware utilization. To address these challenges, we propose a new software technique called thread-level parallelism (TLP) Balancer. TLP Balancer automatically identifies the best-performing number of threads based on performance modeling. This approach significantly enhances hardware utilization and ensures QoS compliance, outperforming traditional fixed-thread allocation methods. Our evaluation shows that TLP Balancer improves throughput by 40% compared to the state-of-the-art automated kernel merge and fusion techniques.
TLP平衡器:嵌入式gpu中多租户推理的预测线程分配
本文介绍了一种新的软件技术,用于在嵌入式图形处理单元(gpu)上的多租户推理系统中优化合并和融合内核的线程分配。配备gpu的嵌入式系统在坚持服务质量(QoS)标准的同时,在管理各种深度学习工作负载方面面临挑战,这主要是由于有限的硬件资源和深度学习模型的各种性质。以前的工作依赖于静态线程分配策略,这通常会导致次优的硬件利用率。为了解决这些挑战,我们提出了一种新的软件技术,称为线程级并行(TLP)平衡器。TLP Balancer根据性能建模自动识别性能最佳的线程数。这种方法显著提高了硬件利用率,并确保了QoS遵从性,优于传统的固定线程分配方法。我们的评估表明,与最先进的自动化内核合并和融合技术相比,TLP Balancer将吞吐量提高了40%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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来源期刊
IEEE Embedded Systems Letters
IEEE Embedded Systems Letters Engineering-Control and Systems Engineering
CiteScore
3.30
自引率
0.00%
发文量
65
期刊介绍: The IEEE Embedded Systems Letters (ESL), provides a forum for rapid dissemination of latest technical advances in embedded systems and related areas in embedded software. The emphasis is on models, methods, and tools that ensure secure, correct, efficient and robust design of embedded systems and their applications.
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