Aditya Anirudh Jonnalagadda;Rishi Thotli;Sreehari Veeramachaneni;Uppugunduru Anil Kumar;Syed Ershad Ahmed
{"title":"优化正数算法的节能解码和编码硬件","authors":"Aditya Anirudh Jonnalagadda;Rishi Thotli;Sreehari Veeramachaneni;Uppugunduru Anil Kumar;Syed Ershad Ahmed","doi":"10.1109/LES.2024.3485002","DOIUrl":null,"url":null,"abstract":"The posit number system represents a binary numerical format devised primarily to mitigate the shortcomings of the IEEE 754 floating-point standard commonly used in modern computer arithmetic. Unlike IEEE 754, which utilizes a fixed-width representation, posits offer a variable-size encoding, dynamically adjusting the number of bits allocated based on the magnitude of the represented number. This adaptability enables posits to provide enhanced precision across a broader range of values, addressing issues like gradual underflow and the multiple representations of zero and NaN values inherent in IEEE 754. However, the dynamic bit allocation also poses significant challenges in decoding the posit number into its constituent fields and packing back the fields of the resultant posit once the arithmetic operations have been performed. For posits to become a viable alternative to floating-points in practical computing systems, the decoding and encoding overheads of posits need to be minimized. Hence, the aim of this letter is to develop energy-efficient hardware for posit decoding and encoding. The proposed <inline-formula> <tex-math>$\\langle 16,2\\rangle $ </tex-math></inline-formula> posit decoders, Decoders A and B show an improvement of over 65% and 33% compared to literature in terms of energy requirements. Similarly, the proposed <inline-formula> <tex-math>$\\langle 16,2\\rangle $ </tex-math></inline-formula> encoder circuit is over 52% more energy-efficient than existing encoder circuits.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"17 3","pages":"131-134"},"PeriodicalIF":2.0000,"publicationDate":"2024-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Energy-Efficient Decoding and Encoding Hardware for Optimized Posit Arithmetic\",\"authors\":\"Aditya Anirudh Jonnalagadda;Rishi Thotli;Sreehari Veeramachaneni;Uppugunduru Anil Kumar;Syed Ershad Ahmed\",\"doi\":\"10.1109/LES.2024.3485002\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The posit number system represents a binary numerical format devised primarily to mitigate the shortcomings of the IEEE 754 floating-point standard commonly used in modern computer arithmetic. Unlike IEEE 754, which utilizes a fixed-width representation, posits offer a variable-size encoding, dynamically adjusting the number of bits allocated based on the magnitude of the represented number. This adaptability enables posits to provide enhanced precision across a broader range of values, addressing issues like gradual underflow and the multiple representations of zero and NaN values inherent in IEEE 754. However, the dynamic bit allocation also poses significant challenges in decoding the posit number into its constituent fields and packing back the fields of the resultant posit once the arithmetic operations have been performed. For posits to become a viable alternative to floating-points in practical computing systems, the decoding and encoding overheads of posits need to be minimized. Hence, the aim of this letter is to develop energy-efficient hardware for posit decoding and encoding. The proposed <inline-formula> <tex-math>$\\\\langle 16,2\\\\rangle $ </tex-math></inline-formula> posit decoders, Decoders A and B show an improvement of over 65% and 33% compared to literature in terms of energy requirements. Similarly, the proposed <inline-formula> <tex-math>$\\\\langle 16,2\\\\rangle $ </tex-math></inline-formula> encoder circuit is over 52% more energy-efficient than existing encoder circuits.\",\"PeriodicalId\":56143,\"journal\":{\"name\":\"IEEE Embedded Systems Letters\",\"volume\":\"17 3\",\"pages\":\"131-134\"},\"PeriodicalIF\":2.0000,\"publicationDate\":\"2024-10-30\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Embedded Systems Letters\",\"FirstCategoryId\":\"94\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10739773/\",\"RegionNum\":4,\"RegionCategory\":\"计算机科学\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q3\",\"JCRName\":\"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Embedded Systems Letters","FirstCategoryId":"94","ListUrlMain":"https://ieeexplore.ieee.org/document/10739773/","RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
Energy-Efficient Decoding and Encoding Hardware for Optimized Posit Arithmetic
The posit number system represents a binary numerical format devised primarily to mitigate the shortcomings of the IEEE 754 floating-point standard commonly used in modern computer arithmetic. Unlike IEEE 754, which utilizes a fixed-width representation, posits offer a variable-size encoding, dynamically adjusting the number of bits allocated based on the magnitude of the represented number. This adaptability enables posits to provide enhanced precision across a broader range of values, addressing issues like gradual underflow and the multiple representations of zero and NaN values inherent in IEEE 754. However, the dynamic bit allocation also poses significant challenges in decoding the posit number into its constituent fields and packing back the fields of the resultant posit once the arithmetic operations have been performed. For posits to become a viable alternative to floating-points in practical computing systems, the decoding and encoding overheads of posits need to be minimized. Hence, the aim of this letter is to develop energy-efficient hardware for posit decoding and encoding. The proposed $\langle 16,2\rangle $ posit decoders, Decoders A and B show an improvement of over 65% and 33% compared to literature in terms of energy requirements. Similarly, the proposed $\langle 16,2\rangle $ encoder circuit is over 52% more energy-efficient than existing encoder circuits.
期刊介绍:
The IEEE Embedded Systems Letters (ESL), provides a forum for rapid dissemination of latest technical advances in embedded systems and related areas in embedded software. The emphasis is on models, methods, and tools that ensure secure, correct, efficient and robust design of embedded systems and their applications.