IEEE Transactions on Advanced Packaging最新文献_第9页

Delay-Based Macromodeling of Long Interconnects From Frequency-Domain Terminal Responses 基于频域终端响应的长互连延迟宏建模

IEEE Transactions on Advanced Packaging Pub Date : 2010-02-01 DOI: 10.1109/TADVP.2008.2010525

A. Chinea, Student Member Ieee Piero Triverio, Senior Member Ieee Stefano Grivet-Talocia

{"title":"Delay-Based Macromodeling of Long Interconnects From Frequency-Domain Terminal Responses","authors":"A. Chinea, Student Member Ieee Piero Triverio, Senior Member Ieee Stefano Grivet-Talocia","doi":"10.1109/TADVP.2008.2010525","DOIUrl":"https://doi.org/10.1109/TADVP.2008.2010525","url":null,"abstract":"We present a robust and efficient scheme for the generation of delay-based macromodels from frequency-domain tabulated responses. These responses can come from both simulation or direct measurement. The main algorithm is based on an iterative weighted least-squares process for the identification of delayed rational approximations. In case that pole relocation is performed during the iterations, the scheme can be interpreted as a generalization of the well-known vector fitting algorithm to delayed systems. Therefore, we denote this algorithm as delayed vector fitting (DVF). In case no pole relocation is performed, the scheme generalizes the so-called Sanathanan-Koerner iteration, calling for the denomination of delayed Sanathanan-Koerner algorithm. These techniques produce compact macromodels that are readily synthesized in SPICE-compatible equivalent circuits including delayed sources or ideal transmission line elements. These macromodels outperform classical rational macromodels in terms of simulation time. Several examples illustrate the advantages of proposed methodology.","PeriodicalId":55015,"journal":{"name":"IEEE Transactions on Advanced Packaging","volume":"220 1","pages":"246-256"},"PeriodicalIF":0.0,"publicationDate":"2010-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TADVP.2008.2010525","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62384152","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 51

Defect Detection of Flip Chip Solder Bumps With Wavelet Analysis of Laser Ultrasound Signals 基于激光超声信号小波分析的倒装芯片焊点缺陷检测

IEEE Transactions on Advanced Packaging Pub Date : 2010-02-01 DOI: 10.1109/TADVP.2009.2034634

Jin Yang, I. C. Ume, Lizheng Zhang

{"title":"Defect Detection of Flip Chip Solder Bumps With Wavelet Analysis of Laser Ultrasound Signals","authors":"Jin Yang, I. C. Ume, Lizheng Zhang","doi":"10.1109/TADVP.2009.2034634","DOIUrl":"https://doi.org/10.1109/TADVP.2009.2034634","url":null,"abstract":"Microelectronics packaging technology has evolved from through-hole and bulk configuration to surface-mount and small-profile ones. In surface mount packaging, such as flip chips, chip scale packages, and ball grid arrays, chips/packages are attached to the substrates/printed wiring board (PWB) using solder bump interconnections. Solder bumps hidden between the chips/packages and the substrate/board are no longer visible for inspection. A novel solder bump inspection system has been developed using laser ultrasound and interferometer techniques. This system has been successfully applied to detect solder bump defects including missing, misaligned, open, and cracked solder bumps in flip chip packages, chip scale packages and land grid arrays. The system uses a pulsed Nd:YAG laser to induce ultrasound in the thermoelastic regime and the transient out-of-plane displacement response in nanometer scale on the package surface is measured using the interferometer technique. In this paper, wavelet analysis of laser ultrasound signals is presented and compared to previous signal processing methods, such as error ratio and correlation coefficient. The results show that wavelet analysis increases measurement sensitivity for inspecting solder bumps in electronic packages. Laser ultrasound inspection results are also compared to X-ray results. In particular, this paper discusses defect detection for a 6.35 mm × 6.35 mm × 0.6 mm PB18 flip chip package and flip chip package (¿SiMAF¿) with 24 lead-free solder bumps. These two types of flip chip specimens are both nonunderfilled.","PeriodicalId":55015,"journal":{"name":"IEEE Transactions on Advanced Packaging","volume":"33 1","pages":"19-29"},"PeriodicalIF":0.0,"publicationDate":"2010-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TADVP.2009.2034634","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62395128","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 19

$z$ -Domain Orthonormal Basis Functions for Physical System Identifications $z$ -物理系统标识的域正交基函数

IEEE Transactions on Advanced Packaging Pub Date : 2010-02-01 DOI: 10.1109/TADVP.2009.2019965

B. Nouri, R. Achar, M. Nakhla

引用次数: 16

Hierarchical Finite-Element Reduction-Recovery Method for Large-Scale Transient Analysis of High-Speed Integrated Circuits 高速集成电路大规模暂态分析的层次有限元还原法

IEEE Transactions on Advanced Packaging Pub Date : 2010-02-01 DOI: 10.1109/TADVP.2009.2019844

H. Gan, D. Jiao

引用次数: 10

Wideband Circuit Model for Planar EBG Structures 平面EBG结构的宽带电路模型

IEEE Transactions on Advanced Packaging Pub Date : 2010-02-01 DOI: 10.1109/TADVP.2009.2021156

B. Mohajer-Iravani, O. Ramahi

引用次数: 45

The Impact of On-Wafer Calibration Method on the Measured Results of Coplanar Waveguide Circuits 片上校准方法对共面波导电路测量结果的影响

IEEE Transactions on Advanced Packaging Pub Date : 2010-02-01 DOI: 10.1109/TADVP.2009.2025365

Qian Li, K. Melde

{"title":"The Impact of On-Wafer Calibration Method on the Measured Results of Coplanar Waveguide Circuits","authors":"Qian Li, K. Melde","doi":"10.1109/TADVP.2009.2025365","DOIUrl":"https://doi.org/10.1109/TADVP.2009.2025365","url":null,"abstract":"This paper compares four commonly used on-wafer calibration methods including multiline thru-reflect-line (TRL), line-reflect-reflect-match, line-reflect-match, and short-open-load- thru, for three diverse coplanar waveguide (CPW) circuits. The magnitudes and phases of S 11 and S 21 of the CPW circuits are compared to quantify how the specific calibration method influences measured scattering parameters. Special care is taken to ensure that the measured scattering parameters are normalized to the same reference impedance and reference plane for accurate comparison. The measured results are compared with full-wave simulations to provide additional assessment of accuracy. A method to de-embed the discontinuity of the CPW at the probe tip and the CPW of the test structures is presented. The effect of probe-to-device-under-test discontinuity is effectively modeled by one- or two- section of shunt capacitor and series inductor. The results show that the multiline TRL calibration method provides the highest transmission coefficient repeatability on not well-matched circuits and highest accuracy on the three circuits in this paper up to 40 GHz.","PeriodicalId":55015,"journal":{"name":"IEEE Transactions on Advanced Packaging","volume":"33 1","pages":"285-292"},"PeriodicalIF":0.0,"publicationDate":"2010-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TADVP.2009.2025365","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62391647","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

Noise Isolation in Mixed-Signal Systems Using Alternating Impedance Electromagnetic Bandgap (AI-EBG) Structure-Based Power Distribution Network (PDN) 基于交流阻抗电磁带隙(AI-EBG)结构的配电网络(PDN)在混合信号系统中的噪声隔离

IEEE Transactions on Advanced Packaging Pub Date : 2010-02-01 DOI: 10.1109/TADVP.2009.2033705

Jinwoo Choi, V. Govind, M. Swaminathan, K. Bharath

{"title":"Noise Isolation in Mixed-Signal Systems Using Alternating Impedance Electromagnetic Bandgap (AI-EBG) Structure-Based Power Distribution Network (PDN)","authors":"Jinwoo Choi, V. Govind, M. Swaminathan, K. Bharath","doi":"10.1109/TADVP.2009.2033705","DOIUrl":"https://doi.org/10.1109/TADVP.2009.2033705","url":null,"abstract":"This paper presents efficient noise isolation and suppression method in mixed-signal systems using alternating impedance electromagnetic bandgap (AI-EBG) structure-based power distribution network (PDN). Currently, split planes are used for isolation in mixed-signal systems for isolating sensitive RF/analog circuits from noisy digital circuits. However, split planes show good isolation only at low frequencies due to electromagnetic coupling through the gap. The AI-EBG structure-based PDN presented in this paper provides excellent isolation (-80 dB ~ -100 dB) in the frequency range of interest by suppressing almost all possible electromagnetic modes. The AI-EBG structure has been integrated into a mixed-signal test vehicle to demonstrate the isolation level achievable. The ability of the AI-EBG structure to suppress switching noise has been quantified in this paper. The AI-EBG structure provided greater than 100 dB of isolation in passive S-parameter measurement and suppressed in-band noise down to -88 dBm of isolation in a functional test.","PeriodicalId":55015,"journal":{"name":"IEEE Transactions on Advanced Packaging","volume":"33 1","pages":"2-12"},"PeriodicalIF":0.0,"publicationDate":"2010-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TADVP.2009.2033705","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62394796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 39

Novel 3-D Coaxial Interconnect System for Use in System-in-Package Applications 用于系统级封装应用的新型三维同轴互连系统

IEEE Transactions on Advanced Packaging Pub Date : 2010-02-01 DOI: 10.1109/TADVP.2009.2033942

B. Lameres, C. McIntosh, M. Abusultan

{"title":"Novel 3-D Coaxial Interconnect System for Use in System-in-Package Applications","authors":"B. Lameres, C. McIntosh, M. Abusultan","doi":"10.1109/TADVP.2009.2033942","DOIUrl":"https://doi.org/10.1109/TADVP.2009.2033942","url":null,"abstract":"This paper presents the design and demonstration of a novel die-to-die interconnect system for deployment in system-in-package (SiP) applications with adjacent or stacked-die configurations. The interconnect system consists of miniature coaxial cables that are mounted to a standard Silicon substrate using an etched trench along the perimeter of the die. The trench serves as a self-alignment feature for both the signal and ground contacts in addition to providing mechanical strain relief for the coaxial cable. The system is designed to interface on-chip coplanar transmission lines to off-chip coaxial transmission lines to produce a fully impedance matched system. This approach promises to dramatically improve the electrical performance of high-speed, die-to-die signals by eliminating impedance discontinuities, providing a shielded signal path, and providing a low-impedance return path for the switching signal. The new interconnect system is designed to be selectively added to a standard wire bond pad configuration using an incremental etching process. This paper describes the design process for the new approach including the fabrication sequence to create the transition trenches. Finite-element analysis is performed to evaluate the electrical performance of the proposed system.","PeriodicalId":55015,"journal":{"name":"IEEE Transactions on Advanced Packaging","volume":"33 1","pages":"37-47"},"PeriodicalIF":0.0,"publicationDate":"2010-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TADVP.2009.2033942","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62395338","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 16

Fast Reduced-Order Finite-Element Modeling of Lossy Thin Wires Using Lumped Impedance Elements 基于集总阻抗元件的有损细导线快速降阶有限元建模

IEEE Transactions on Advanced Packaging Pub Date : 2010-02-01 DOI: 10.1109/TADVP.2009.2015958

Shih-Hao Lee, Jianming Jin

引用次数: 7

Reliability Verification of Hermetic Package With Nanoliter Cavity for RF-Micro Device 射频微器件用纳升腔密封封装可靠性验证

IEEE Transactions on Advanced Packaging Pub Date : 2010-02-01 DOI: 10.1109/TADVP.2009.2019843

Byung-gil Jeong, S. Ham, Chang-youl Moon, Byung-Sung Kim

{"title":"Reliability Verification of Hermetic Package With Nanoliter Cavity for RF-Micro Device","authors":"Byung-gil Jeong, S. Ham, Chang-youl Moon, Byung-Sung Kim","doi":"10.1109/TADVP.2009.2019843","DOIUrl":"https://doi.org/10.1109/TADVP.2009.2019843","url":null,"abstract":"With the advance of high-performance and small-size microelectromechanical systems (MEMS) devices, wafer-level packaging has gained increased attention over the past few years. Most MEMS packages must protect the often-fragile mechanical structures against the environment and provide the interface for the interaction with the next level in the packaging hierarchy. It is obvious that stable performance and high reliability are essential requirements of a packaged device. In this paper, a novel hermetic package, called the WL-¿P, recently developed for radio-frequency (RF)-filter and RF-duplexer, will be reviewed in terms of its construction, fabrication process, and electrical/mechanical performance. The package consists of a device wafer for a MEMS device and a cap wafer that has a micromachined cavity and through-wafer vias for electrical connections. The cap and device wafers are bonded to each other through a closed square loop of gold/tin eutectic solder at the peripheral edge. The via-in-cavity structure is designed in the cap substrate, with vertical via holes fabricated and fully electroplated with copper. The detailed design and fabrication technology of this new type of hermetically sealed package are presented with process flow. The performance evaluation and reliability results of a hermetic package will also be presented. The developed wafer-level hermetic package technology is able to fulfill today's requirements for hermetic and cost-effective packaging of high-speed RF-MEMS applications.","PeriodicalId":55015,"journal":{"name":"IEEE Transactions on Advanced Packaging","volume":"33 1","pages":"64-71"},"PeriodicalIF":0.0,"publicationDate":"2010-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TADVP.2009.2019843","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62390142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5