IEEE Transactions on Advanced Packaging最新文献_第10页

Parallel Simulation of Massively Coupled Interconnect Networks 大规模耦合互连网络的并行仿真

IEEE Transactions on Advanced Packaging Pub Date : 2010-02-01 DOI: 10.1109/TADVP.2009.2025263

D. Paul, N. Nakhla, R. Achar, M. Nakhla

引用次数: 23

Time Domain Delay Extraction-Based Macromodeling Algorithm for Long-Delay Networks 基于时域延迟提取的长时延网络宏建模算法

IEEE Transactions on Advanced Packaging Pub Date : 2010-02-01 DOI: 10.1109/TADVP.2009.2029560

A. Charest, M. Nakhla, R. Achar, D. Saraswat, N. Soveiko, I. Erdin

引用次数: 33

LTCC Spiral Inductor Synthesis and Optimization With Measurement Verification LTCC螺旋电感的合成与优化及测量验证

IEEE Transactions on Advanced Packaging Pub Date : 2010-02-01 DOI: 10.1109/TADVP.2009.2028636

Hsin-Chia Lu, T. Chan, C. Chen, Chia-Ming Liu, Heng-Jui Hsing, Po-Sheng Huang

引用次数: 20

Escape Routing in Modern Area Array Packaging: An Analysis of Need, Trend, and Capability 现代区域阵列封装中的逃逸路径:需求、趋势与能力分析

IEEE Transactions on Advanced Packaging Pub Date : 2010-02-01 DOI: 10.1109/TADVP.2009.2035304

B. Jaiswal, M. Roy, A. Titus

{"title":"Escape Routing in Modern Area Array Packaging: An Analysis of Need, Trend, and Capability","authors":"B. Jaiswal, M. Roy, A. Titus","doi":"10.1109/TADVP.2009.2035304","DOIUrl":"https://doi.org/10.1109/TADVP.2009.2035304","url":null,"abstract":"With the increasing complexity in the die and package designs and ever increasing cost pressure in today's microelectronic industry, the design for input/output (I/O) routing has assumed a vital role in the overall product design. This scenario is primarily driven by the increase in the I/O terminal counts in both die and package. Several authors have already described the possibility of using various escape routing models in order to maximize the number of I/Os in a given area. However, these models suffer from many drawbacks and fail to address the importance of processing factors and the actual manufacturing conditions. Therefore, a new design guideline for escape routing has been developed to achieve the maximum I/O density under the actual manufacturing, processing and cost related constraints. The correlation between the real world constraints and their impact on I/O routing has been explored and used as a foundation for developing design guidelines. This approach has been presented through a comprehensive case study that covers various design scenarios, provides the right set of real world trade-offs that need to be considered and simultaneously highlights the drawbacks in existing models.","PeriodicalId":55015,"journal":{"name":"IEEE Transactions on Advanced Packaging","volume":"33 1","pages":"13-18"},"PeriodicalIF":0.0,"publicationDate":"2010-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TADVP.2009.2035304","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62395886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

On-Chip Coupled Transmission Line Modeling for Millimeter-Wave Applications Using Four-Port Measurements 片上耦合传输线建模毫米波应用使用四端口测量

IEEE Transactions on Advanced Packaging Pub Date : 2010-02-01 DOI: 10.1109/TADVP.2009.2024212

K. Kang, J. Brinkhoff, Jinglin Shi, F. Lin

引用次数: 28

Electromigration Characteristic of SnAg $_{3.0}$ Cu $_{0.5}$ Flip Chip Interconnection SnAg $ {3.0}$ Cu ${0.5}$倒装芯片互连的电迁移特性

IEEE Transactions on Advanced Packaging Pub Date : 2010-02-01 DOI: 10.1109/TADVP.2009.2033941

Chien-Chen Lee, Chang-Chun Lee, K. Chiang

{"title":"Electromigration Characteristic of SnAg $_{3.0}$ Cu $_{0.5}$ Flip Chip Interconnection","authors":"Chien-Chen Lee, Chang-Chun Lee, K. Chiang","doi":"10.1109/TADVP.2009.2033941","DOIUrl":"https://doi.org/10.1109/TADVP.2009.2033941","url":null,"abstract":"Electromigration is a reliability concern of microelectronic interconnections, especially for flip chip solder bump with high current density applied. This study shows that with the line-to-bump geometry in a flip chip solder joint, the current density changes significantly between the Al trace and the bump, while the current crowding effect generates more heat between them. This large Joule heating under high current density can enhance the migration of Sn atoms at the current entrance of the solder bump, and cause the void formation at the entrance point. The present study finds two kinds of electromigration failure modes at the cathode/chip side of the solder bump: the pancake-type and the cotton-type void. The experimental finding shows that the effects of polarity and tilting are key factors to observe in the electromigration behavior of SnAg3.0Cu0.5 solder bumps. Consequently, this study has designed a 3-D numerical model and a corresponding test vehicle to verify the numerical finding. The maximum current density is simulated through the finite element method to provide a better understanding of local heat and current crowding. This study finds that the current crowding ratio is reduced linearly while the void formation is increased. Furthermore, it is concluded that there is a linear relationship between the growth of the intermetallic compound (IMC) layer and the applied current density at the anode/substrate side.","PeriodicalId":55015,"journal":{"name":"IEEE Transactions on Advanced Packaging","volume":"33 1","pages":"189-195"},"PeriodicalIF":0.0,"publicationDate":"2010-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TADVP.2009.2033941","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62394826","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Analysis of Adhesion and Fracture Energy of Nano-Particle Silver in Electronics Packaging Applications 纳米银在电子封装中的粘附和断裂能分析

IEEE Transactions on Advanced Packaging Pub Date : 2010-02-01 DOI: 10.1109/TADVP.2009.2033809

Sungchul Joo, D. Baldwin

{"title":"Analysis of Adhesion and Fracture Energy of Nano-Particle Silver in Electronics Packaging Applications","authors":"Sungchul Joo, D. Baldwin","doi":"10.1109/TADVP.2009.2033809","DOIUrl":"https://doi.org/10.1109/TADVP.2009.2033809","url":null,"abstract":"Nano-particle silver (NPS) conductors are increasingly being investigated for package level electronics applications. Unlike traditional thick film materials and conductive inks, nano-particle conductors often do not incorporate compounds to promote interfacial adhesion such as binders used in thick films and polymer adhesives used in conductive inks as these adhesion promoters can degrade the electrical performance. The NPS is concerned with low adhesion to most of processed polymer surface such as liquid crystal polymer (LCP), polyimide, and benzocyclobutene (BCB). Moreover, the adhesion mechanism of NPS has not been identified yet. Thus, as a first step to identify NPS adhesion mechanism and thus, to improve NPS adhesion, quantitative measurement of the adhesion strength of NPS is necessary. Since conventional adhesion test methods are not directly applicable to thin (~ 2 ¿m) NPS film adhesion test, a new adhesion test method is developed in this paper to estimate the adhesion strength of NPS films. The newly developed adhesion test method is called modified button shear test (MBST) because it modifies the conventional button shear test and integrates the generally known die shear test. The MBST is used for measuring not only interfacial bond strength, but also interfacial fracture energy. The interfacial bond strength in tension and the interfacial fracture energy of NPS with LCP substrate measured by MBST are 24.4 MPa and 17.2 J/m2, respectively. The MBST is generic in nature and can be extended to other thin films adhesion test for measuring interfacial bond strength and interfacial fracture energy.","PeriodicalId":55015,"journal":{"name":"IEEE Transactions on Advanced Packaging","volume":"33 1","pages":"48-57"},"PeriodicalIF":0.0,"publicationDate":"2010-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TADVP.2009.2033809","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62394969","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 15

Design and Fabrication of 0/1-Level RF-Via Interconnect for RF-MEMS Packaging Applications RF-MEMS封装应用中0/1级RF-Via互连的设计与制造

IEEE Transactions on Advanced Packaging Pub Date : 2010-02-01 DOI: 10.1109/TADVP.2009.2034137

Li-Han Hsu, Wei-Cheng Wu, E. Chang, H. Zirath, Yun-Chi Wu, Chin-Te Wang, Ching-Ting Lee

引用次数: 8

Design and Implementation of a Novel Hybrid Photonic Crystal Power/Ground Layer for Broadband Power Noise Suppression 一种新型混合光子晶体功率/接地层的设计与实现，用于宽带功率噪声抑制

IEEE Transactions on Advanced Packaging Pub Date : 2010-02-01 DOI: 10.1109/TADVP.2009.2034334

Guanqun Wu, Yi-Che Chen, Tzong-Lin Wu

{"title":"Design and Implementation of a Novel Hybrid Photonic Crystal Power/Ground Layer for Broadband Power Noise Suppression","authors":"Guanqun Wu, Yi-Che Chen, Tzong-Lin Wu","doi":"10.1109/TADVP.2009.2034334","DOIUrl":"https://doi.org/10.1109/TADVP.2009.2034334","url":null,"abstract":"By embedding periodically high-K rods in the package substrate, a hybrid photonic crystal power/ground layers (PCPL) is proposed with stopband enhancement for power/ground noise suppression. The hybrid PCPL consists of two different lattice structures, which have the same pitch but different radii of the high-K rods. Using the gap map of the photonic crystal lattice, the enhanced stopband can be synthesized by designing these two different lattices with compensated stopband. An implementation approach, which is compatible to the standard fabrication process of package or printed circuit board (PCB), is also proposed in this paper. The high-K rods are considered as surface mount technology (SMT)-like components and ring-shaped soldering pads with through-hole-via connecting to power/ground planes are designed on the package substrate. A test sample of the hybrid PCPL is fabricated and measured. A wide stopband from 3.2 to 9.5 GHz is achieved with 30 dB of noise suppression in average. This enhanced stopband is consistent with the prediction both by gap map synthesis and full-wave simulation. The hybrid PCPL is applied in a package substrate with voltage-controlled oscillator (VCO) circuit and excellent noise suppression performance is demonstrated.","PeriodicalId":55015,"journal":{"name":"IEEE Transactions on Advanced Packaging","volume":"33 1","pages":"206-211"},"PeriodicalIF":0.0,"publicationDate":"2010-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TADVP.2009.2034334","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62395052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 19

Fast Reduction Algorithms in the Frequency-Domain Layered Finite Element Method for the Electromagnetic Analysis of Large-Scale High-Frequency Integrated Circuits 大规模高频集成电路电磁分析的频域分层有限元快速约简算法

IEEE Transactions on Advanced Packaging Pub Date : 2010-02-01 DOI: 10.1109/TADVP.2009.2014353

Feng Sheng, D. Jiao

引用次数: 2