{"title":"Novel 3-D Coaxial Interconnect System for Use in System-in-Package Applications","authors":"B. Lameres, C. McIntosh, M. Abusultan","doi":"10.1109/TADVP.2009.2033942","DOIUrl":null,"url":null,"abstract":"This paper presents the design and demonstration of a novel die-to-die interconnect system for deployment in system-in-package (SiP) applications with adjacent or stacked-die configurations. The interconnect system consists of miniature coaxial cables that are mounted to a standard Silicon substrate using an etched trench along the perimeter of the die. The trench serves as a self-alignment feature for both the signal and ground contacts in addition to providing mechanical strain relief for the coaxial cable. The system is designed to interface on-chip coplanar transmission lines to off-chip coaxial transmission lines to produce a fully impedance matched system. This approach promises to dramatically improve the electrical performance of high-speed, die-to-die signals by eliminating impedance discontinuities, providing a shielded signal path, and providing a low-impedance return path for the switching signal. The new interconnect system is designed to be selectively added to a standard wire bond pad configuration using an incremental etching process. This paper describes the design process for the new approach including the fabrication sequence to create the transition trenches. Finite-element analysis is performed to evaluate the electrical performance of the proposed system.","PeriodicalId":55015,"journal":{"name":"IEEE Transactions on Advanced Packaging","volume":"33 1","pages":"37-47"},"PeriodicalIF":0.0000,"publicationDate":"2010-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TADVP.2009.2033942","citationCount":"16","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Advanced Packaging","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/TADVP.2009.2033942","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 16
Abstract
This paper presents the design and demonstration of a novel die-to-die interconnect system for deployment in system-in-package (SiP) applications with adjacent or stacked-die configurations. The interconnect system consists of miniature coaxial cables that are mounted to a standard Silicon substrate using an etched trench along the perimeter of the die. The trench serves as a self-alignment feature for both the signal and ground contacts in addition to providing mechanical strain relief for the coaxial cable. The system is designed to interface on-chip coplanar transmission lines to off-chip coaxial transmission lines to produce a fully impedance matched system. This approach promises to dramatically improve the electrical performance of high-speed, die-to-die signals by eliminating impedance discontinuities, providing a shielded signal path, and providing a low-impedance return path for the switching signal. The new interconnect system is designed to be selectively added to a standard wire bond pad configuration using an incremental etching process. This paper describes the design process for the new approach including the fabrication sequence to create the transition trenches. Finite-element analysis is performed to evaluate the electrical performance of the proposed system.