IEEE Transactions on Advanced Packaging最新文献

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An Integration Technology for RF and Microwave Circuits Based on Interconnect Programming 基于互连编程的射频与微波电路集成技术
IEEE Transactions on Advanced Packaging Pub Date : 2010-02-25 DOI: 10.1109/TADVP.2009.2038234
L. Rabieirad, E. Martinez, S. Mohammadi
{"title":"An Integration Technology for RF and Microwave Circuits Based on Interconnect Programming","authors":"L. Rabieirad, E. Martinez, S. Mohammadi","doi":"10.1109/TADVP.2009.2038234","DOIUrl":"https://doi.org/10.1109/TADVP.2009.2038234","url":null,"abstract":"A configurable integration technology suitable for implementing application specific radio-frequency (RF) and microwave circuits is presented. This postfabrication integration scheme is compatible with complementary metal-oxide-semiconductor (CMOS) technology and utilizes room temperature deposited Parylene-N as low loss and low permittivity dielectric material. Interconnect lines, inductors, and transmission lines fabricated on top of arrays of prefabricated 0.13 ¿m and 90 nm CMOS transistors coated with Parylene-N are configured to design interconnect programmable RF and microwave circuits. The technology is used to demonstrate three proof of concept interconnect programmable narrowband amplifiers. These amplifiers have center frequencies of 5.5, 6.4, and 18 GHz with forward gain S21 of 16.6, 11, and 18.7 dB, respectively. Fabrication simplicity and programmable nature of this technology compared to standard application specific integrated circuit (ASIC) fabrication lowers the cost and time to market of individual ASIC chip.","PeriodicalId":55015,"journal":{"name":"IEEE Transactions on Advanced Packaging","volume":"13 1","pages":"362-369"},"PeriodicalIF":0.0,"publicationDate":"2010-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TADVP.2009.2038234","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62395798","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Aligning Chips Face-to-Face for Dense Capacitive and Optical Communication 面向密集电容和光通信的芯片面对面对齐
IEEE Transactions on Advanced Packaging Pub Date : 2010-02-25 DOI: 10.1109/TADVP.2009.2037437
J. Cunningham, A. Krishnamoorthy, I. Shubin, Xuezhe Zheng, M. Asghari, D. Feng, James G. Mitchell
{"title":"Aligning Chips Face-to-Face for Dense Capacitive and Optical Communication","authors":"J. Cunningham, A. Krishnamoorthy, I. Shubin, Xuezhe Zheng, M. Asghari, D. Feng, James G. Mitchell","doi":"10.1109/TADVP.2009.2037437","DOIUrl":"https://doi.org/10.1109/TADVP.2009.2037437","url":null,"abstract":"We report a new method that precisely self-aligns face-to-face semiconductor chips or wafers to enable communication between the chips using electromagnetic waves. Our alignment mechanism takes advantage of miniaturized versions of two of nature's idealized shapes: an inverse pyramidal shape defined by a self-terminating wet-etch process in silicon and micro-spheres with radii accurate to submicron accuracy. This approach allows chips to be packaged using passive alignment that is self locating and reaches nearly one micron level of chip misalignment tolerance. Packages for applications to capacitive and optical connections are presented. Additionally, we describe a physical architecture for a multi-chip array packages with ¿bridge¿ and ¿island¿ chips where the function of the bridge is to transfer electromagnetic signals between island chips using either capacitive or optical proximity communication. The bridge chip can provide a predetermined amount of compliance to help maintain alignment and thereby accommodate topology variants in first level package or in chip thickness when required. Experimental packages providing precise alignment between 1-D arrays and 2-D arrays of chips are presented. We show that our precision alignment mechanism enables high fidelity 10 Gb/s optical-proximity-communication with reflecting mirrors micro-machined into Silicon and co-integrated to low loss silicon-on-insulator waveguides for chip-to-chip communication. The alignment mechanism was also applied to a demonstration of chip-to-chip capacitive proximity communication in a linear array of six chips. Alignment measurements on a 4 × 4 array of chips are reported.","PeriodicalId":55015,"journal":{"name":"IEEE Transactions on Advanced Packaging","volume":"33 1","pages":"389-397"},"PeriodicalIF":0.0,"publicationDate":"2010-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TADVP.2009.2037437","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62395974","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Component Tolerance Effect on Ultra-Wideband Low-Noise Amplifier Performance 元件容差对超宽带低噪声放大器性能的影响
IEEE Transactions on Advanced Packaging Pub Date : 2010-02-25 DOI: 10.1109/TADVP.2010.2041348
A. Serban, M. Karlsson, Shaofang Gong
{"title":"Component Tolerance Effect on Ultra-Wideband Low-Noise Amplifier Performance","authors":"A. Serban, M. Karlsson, Shaofang Gong","doi":"10.1109/TADVP.2010.2041348","DOIUrl":"https://doi.org/10.1109/TADVP.2010.2041348","url":null,"abstract":"A study of the component tolerances on an ultra-wideband (UWB) low-noise amplifier designed on a conventional printed circuit board is presented in this paper. The low-noise amplifier design employs dual-section input and output microstrip matching networks for wideband operation with a low noise figure and a flat power gain. First, the effect of passive component and manufacturing process tolerances on the low-noise amplifier performance is theoretically studied by means of sensitivity analyses. Second, simulation and measurement results are presented for verification of the analytical results. It is shown that, compared with a lumped matching network design, a microstrip matching network design significantly reduces the UWB low-noise amplifier sensitivity to component tolerances.","PeriodicalId":55015,"journal":{"name":"IEEE Transactions on Advanced Packaging","volume":"33 1","pages":"660-668"},"PeriodicalIF":0.0,"publicationDate":"2010-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TADVP.2010.2041348","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62396608","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Packaging of Dual-Mode Wireless Communication Module Using RF/Optoelectronic Devices With Shared Functional Components 利用共享功能元件的射频/光电器件封装双模无线通信模块
IEEE Transactions on Advanced Packaging Pub Date : 2010-02-17 DOI: 10.1109/TADVP.2009.2038359
J. Liao, J. Zeng, Shengling Deng, A. Boryssenko, V. Joyner, Z. Huang
{"title":"Packaging of Dual-Mode Wireless Communication Module Using RF/Optoelectronic Devices With Shared Functional Components","authors":"J. Liao, J. Zeng, Shengling Deng, A. Boryssenko, V. Joyner, Z. Huang","doi":"10.1109/TADVP.2009.2038359","DOIUrl":"https://doi.org/10.1109/TADVP.2009.2038359","url":null,"abstract":"This paper reports the design, fabrication, and testing of a compact radio-frequency (RF)/ free space optical (FSO) dual mode wireless communication system. A modified split dual-director quasi-Yagi antenna is integrated with optical transmitter and receiver by sharing layout structural components. Bare die vertical-cavity surface-emitting laser (VCSEL) and P-i-N photodiode (PIN) are placed on antenna director pads and wire bonded to printed circuit board (PCB)-mounted laser driver and transimpedance amplifier (TIA) circuits. Detailed analysis of coupling between RF channel and associated electrical connections for the FSO channel is presented using commercial simulation tools to predict its impact on link degradation. Although crosstalk appears between RF and optical channels, the prototyped system demonstrated dual-mode high-rate communication capability with measured 2.5 Gb/s data rate in FSO link. Variations in RF subsystem features due to coupling from the FSO subsystem is estimated through radiation pattern measurement using near-field scanner.","PeriodicalId":55015,"journal":{"name":"IEEE Transactions on Advanced Packaging","volume":"33 1","pages":"323-332"},"PeriodicalIF":0.0,"publicationDate":"2010-02-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TADVP.2009.2038359","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62396251","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
GaN-Based Power Flip-Chip LEDs With an Internal ESD Protection Diode on Cu Sub-Mount 基于gan的内置ESD保护二极管的电源倒装led
IEEE Transactions on Advanced Packaging Pub Date : 2010-02-02 DOI: 10.1109/TADVP.2009.2037806
Y. X. Sun, W. Chen, S. Hung, K. Lam, C. H. Liu, S. Chang
{"title":"GaN-Based Power Flip-Chip LEDs With an Internal ESD Protection Diode on Cu Sub-Mount","authors":"Y. X. Sun, W. Chen, S. Hung, K. Lam, C. H. Liu, S. Chang","doi":"10.1109/TADVP.2009.2037806","DOIUrl":"https://doi.org/10.1109/TADVP.2009.2037806","url":null,"abstract":"The authors demonstrate the fabrication of 1 mm × 1 mm GaN-based power flip-chip light-emitting diodes (LEDs) with an internal electrostatic discharge (ESD) protection diode on Cu sub-mount. With the internal diode, it was found that forward voltage of the LED increased from 3.22 to 3.38 V while output power decreased from 366.5 to 273.9 mW when under 350 mA current injection due to the reduced light emitting area. It was also found that we can achieve a significantly better ESD robustness by building the internal diode inside the LED chip. Furthermore, It was found that 90% of the LEDs with internal diode survived with an applied reverse ESD surge of 12000 V and 25% of the LEDs can even endure 20000 V reverse ESD stressing.","PeriodicalId":55015,"journal":{"name":"IEEE Transactions on Advanced Packaging","volume":"33 1","pages":"433-437"},"PeriodicalIF":0.0,"publicationDate":"2010-02-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TADVP.2009.2037806","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62395753","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
The Investigation of Nano-Roughening Effect on the Reliability Enhancement of Adhesive Bond for NEMS Manufacture Application 纳米粗化对NEMS制造中粘合剂可靠性提高的影响研究
IEEE Transactions on Advanced Packaging Pub Date : 2010-02-02 DOI: 10.1109/TADVP.2009.2038235
Chia-Yeh Yang, Yu-Ting Cheng, W. Hsu
{"title":"The Investigation of Nano-Roughening Effect on the Reliability Enhancement of Adhesive Bond for NEMS Manufacture Application","authors":"Chia-Yeh Yang, Yu-Ting Cheng, W. Hsu","doi":"10.1109/TADVP.2009.2038235","DOIUrl":"https://doi.org/10.1109/TADVP.2009.2038235","url":null,"abstract":"The paper shows the importance of nano-roughening on the bonding interface to the reliability enhancement of adhesive bond for ensuring the continuation of packaging shrinkage from MEMS to NEMS. The roughening is realized via a nonuniformly etching characteristic of PR which is etched and then utilized as an etching mask for following silicon etching process. Ultraviolet adhesive for silicon-to-glass bonding is utilized for the verification of the nano-roughening effect on NEMS hermetic encapsulation. The average roughnesses of the silicon substrate before and after roughening are 0.4 nm and 12.4 nm, respectively. Experimental results show that the roughness increase of silicon substrate can effectively provide more than 30% bonding strength enhancement and 30% leakage reduction. In addition, stamp-and-stick test shows that nano-roughening indeed provides a better adhesive characteristic that can further ensure the success of the stamp-and-stick process for nano/microfabrication.","PeriodicalId":55015,"journal":{"name":"IEEE Transactions on Advanced Packaging","volume":"33 1","pages":"356-361"},"PeriodicalIF":0.0,"publicationDate":"2010-02-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TADVP.2009.2038235","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62395861","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Enhanced Microstrip Guard Trace for Ringing Noise Suppression Using a Dielectric Superstrate 利用介电层抑制振铃噪声的增强型微带保护走线
IEEE Transactions on Advanced Packaging Pub Date : 2010-02-02 DOI: 10.1109/TADVP.2010.2040033
Yung-Shou Cheng, Wei-Da Guo, C. Hung, R. Wu, D. De Zutter
{"title":"Enhanced Microstrip Guard Trace for Ringing Noise Suppression Using a Dielectric Superstrate","authors":"Yung-Shou Cheng, Wei-Da Guo, C. Hung, R. Wu, D. De Zutter","doi":"10.1109/TADVP.2010.2040033","DOIUrl":"https://doi.org/10.1109/TADVP.2010.2040033","url":null,"abstract":"Grounded guard traces are increasingly used to reduce the coupling-induced crosstalk, but the incurred ringing noise will strongly limit the performance for the microstrip structures. This paper describes the generation mechanism of the ringing noise and derives an analytical formula of the noise magnitude. Besides, an enhanced microstrip guard trace design is proposed to eliminate the ringing noise by covering the original microstrip structure with a superstrate of higher permittivity. A design space versus the superstrate thickness and the dielectric constant are constructed and in which, the guard trace needs be grounded at the two ends only without causing any ringing noise. Finally, the time-domain simulations and experiments are performed to verify the proposed concept.","PeriodicalId":55015,"journal":{"name":"IEEE Transactions on Advanced Packaging","volume":"33 1","pages":"961-968"},"PeriodicalIF":0.0,"publicationDate":"2010-02-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TADVP.2010.2040033","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62396093","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 26
Fine-Pitch Capabilities of the Flat Ultra-Thin Chip Packaging (UTCP) Technology 扁平超薄芯片封装(UTCP)技术的细间距性能
IEEE Transactions on Advanced Packaging Pub Date : 2010-02-01 DOI: 10.1109/TADVP.2009.2018134
J. Govaerts, E. Bosman, W. Christiaens, J. Vanfleteren
{"title":"Fine-Pitch Capabilities of the Flat Ultra-Thin Chip Packaging (UTCP) Technology","authors":"J. Govaerts, E. Bosman, W. Christiaens, J. Vanfleteren","doi":"10.1109/TADVP.2009.2018134","DOIUrl":"https://doi.org/10.1109/TADVP.2009.2018134","url":null,"abstract":"This paper describes the fine-pitch interconnection capabilities of the ultra-thin chip packaging (UTCP) technology, a technology under development for embedding thin chips in a flexible polyimide (PI) substrate. It allows for fully flexible electronics, as the rigid chips are thinned down to 20-30 ¿m, at which point they become truly flexible themselves. This way, instead of just a flexible substrate with rigid components assembled on top, the entire circuitry can be incorporated inside a 30-40 ¿m thin chip package. The paper briefly introduces the technology's background with a short description of the fabrication process. Building on the developments already achieved, some further optimizations are discussed, and the technology is tested for its fine-pitch interconnection capabilities using test chips with four-point probe and daisy chain patterns, with a pitch down to 40 ¿m. The possibility to package several chips in the same substrate is investigated, as well, and finally an outlook on future experiments is briefly discussed.","PeriodicalId":55015,"journal":{"name":"IEEE Transactions on Advanced Packaging","volume":"33 1","pages":"72-78"},"PeriodicalIF":0.0,"publicationDate":"2010-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TADVP.2009.2018134","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62388595","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Characterization of Next Generation Thin Low-K and Low-Loss Organic Dielectrics From 1 to 110 GHz 1 ~ 110 GHz新一代薄低k低损耗有机介质的特性研究
IEEE Transactions on Advanced Packaging Pub Date : 2010-02-01 DOI: 10.1109/TADVP.2009.2023413
Seunghyun Hwang, S. Min, Madhavan Swaminathan, Venkatesan Venkatakrishnan, H. Chan, Fuhan Liu, V. Sundaram, S. Kennedy, D. Baars, B. Lacroix, Yuan Li, J. Papapolymerou
{"title":"Characterization of Next Generation Thin Low-K and Low-Loss Organic Dielectrics From 1 to 110 GHz","authors":"Seunghyun Hwang, S. Min, Madhavan Swaminathan, Venkatesan Venkatakrishnan, H. Chan, Fuhan Liu, V. Sundaram, S. Kennedy, D. Baars, B. Lacroix, Yuan Li, J. Papapolymerou","doi":"10.1109/TADVP.2009.2023413","DOIUrl":"https://doi.org/10.1109/TADVP.2009.2023413","url":null,"abstract":"This paper presents, for the first time, characterization results of next generation dielectric core and build up material called RXP, which has low dielectric constant (2.93-3.48) and low loss tangent (0.0037-0.006) up to 110 GHz. Unlike LCP, this material can be made ultra-thin with low processing temperature and is ideally suited for mobile applications. Causal models suitable for high frequency applications have been extracted by measuring the response of cavity resonators using vector network analyzer and surface profiler.","PeriodicalId":55015,"journal":{"name":"IEEE Transactions on Advanced Packaging","volume":"43 1","pages":"180-188"},"PeriodicalIF":0.0,"publicationDate":"2010-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TADVP.2009.2023413","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62391082","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
Fast Passivity Enforcement for S-Parameter Models by Perturbation of Residue Matrix Eigenvalues 基于剩余矩阵特征值摄动的s参数模型快速无源增强
IEEE Transactions on Advanced Packaging Pub Date : 2010-02-01 DOI: 10.1109/TADVP.2008.2010508
B. Gustavsen
{"title":"Fast Passivity Enforcement for S-Parameter Models by Perturbation of Residue Matrix Eigenvalues","authors":"B. Gustavsen","doi":"10.1109/TADVP.2008.2010508","DOIUrl":"https://doi.org/10.1109/TADVP.2008.2010508","url":null,"abstract":"Rational macromodels must be passive in order to guarantee a stable simulation. This paper introduces a fast approach for enforcing passivity for S-parameter based pole-residue models, using a similar method previously introduced for Y-parameter models. The approach is based on perturbing the elements of the residue matrices with the perturbed residue matrix eigenvalues as free variables. This gives large savings for the CPU time and memory requirements. The implementation does not require sparse computations. Combining the passivity enforcement step with iterations and fast passivity assessment via a half-size test matrix gives a globally passive model. Error control strategies are implemented via least squares weighting. The approach is demonstrated for a two-port microwave filter, a four-port interconnect, a 48-port low-order package model, and a 28-port high-order package model.","PeriodicalId":55015,"journal":{"name":"IEEE Transactions on Advanced Packaging","volume":"33 1","pages":"257-265"},"PeriodicalIF":0.0,"publicationDate":"2010-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TADVP.2008.2010508","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62384027","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 75
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