2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC)最新文献_第2页

A Transferable GNN-based Multi-Corner Performance Variability Modeling for Analog ICs 基于可转移 GNN 的模拟集成电路多角度性能变异性建模

2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2024-01-22 DOI: 10.1109/ASP-DAC58780.2024.10473858

Hongjian Zhou, Yaguang Li, Xin Xiong, Pingqiang Zhou

引用次数: 0

ASP-DAC 2024 Cover Page ASP-DAC 2024 封面页

2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2024-01-22 DOI: 10.1109/asp-dac58780.2024.10473969

引用次数: 0

Adaptive Control-Logic Routing for Fully Programmable Valve Array Biochips Using Deep Reinforcement Learning 利用深度强化学习为完全可编程阀门阵列生物芯片提供自适应控制逻辑路由选择

2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2024-01-22 DOI: 10.1109/ASP-DAC58780.2024.10473962

Huayang Cai, Genggeng Liu, Wenzhong Guo, Zipeng Li, Tsung-Yi Ho, Xing Huang

{"title":"Adaptive Control-Logic Routing for Fully Programmable Valve Array Biochips Using Deep Reinforcement Learning","authors":"Huayang Cai, Genggeng Liu, Wenzhong Guo, Zipeng Li, Tsung-Yi Ho, Xing Huang","doi":"10.1109/ASP-DAC58780.2024.10473962","DOIUrl":"https://doi.org/10.1109/ASP-DAC58780.2024.10473962","url":null,"abstract":"With the increasing integration level of flow-based microfluidics, fully programmable valve arrays (FPVAs) have emerged as the next generation of microfluidic devices. Mi-crovalves in an FPVA are typically managed by a control logic, where valves are connected to a core input via control channels to receive control signals that guide states switching. The critical valves that suffer from asynchronous actuation leading to chip malfunctions, however, need to be switched simultaneously in a specific bioassay. As a result, the channel lengths from the core input to these valves are required to be equal or similar, which poses a challenge to the channel routing of the control logic. To solve this problem, we propose a deep reinforcement learning-based adaptive routing flow for the control logic of FPVAs. With the proposed routing flow, an efficient control channel network can be automatically constructed to realize accurate control signals propagation. Meanwhile, the timing skews among synchronized valves and the total length of control channels can be minimized, thus generating an optimized control logic with excellent timing behavior. Simulation results on multiple benchmarks demonstrate the effectiveness of the proposed routing flow.","PeriodicalId":518586,"journal":{"name":"2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"55 3-4","pages":"564-569"},"PeriodicalIF":0.0,"publicationDate":"2024-01-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140530930","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

BNN-Flip: Enhancing the Fault Tolerance and Security of Compute-in-Memory Enabled Binary Neural Network Accelerators BNN-Flip：增强支持内存计算的二元神经网络加速器的容错性和安全性

2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2024-01-22 DOI: 10.1109/ASP-DAC58780.2024.10473947

Akul Malhotra, Chunguang Wang, Sumeet Kumar Gupta

{"title":"BNN-Flip: Enhancing the Fault Tolerance and Security of Compute-in-Memory Enabled Binary Neural Network Accelerators","authors":"Akul Malhotra, Chunguang Wang, Sumeet Kumar Gupta","doi":"10.1109/ASP-DAC58780.2024.10473947","DOIUrl":"https://doi.org/10.1109/ASP-DAC58780.2024.10473947","url":null,"abstract":"Compute-in-memory based binary neural networks or CiM-BNNs offer high energy/area efficiency for the design of edge deep neural network (DNN) accelerators, with only a mild accuracy reduction. However, for successful deployment, the design of CiM-BNNs must consider challenges such as memory faults and data security that plague existing DNN accelerators. In this work, we aim to mitigate both these problems simultaneously by proposing BNN-Flip, a training-free weight transformation algorithm that not only enhances the fault tolerance of CiM-BNNs but also protects them from weight theft attacks. BNN-Flip inverts the rows and columns of the BNN weight matrix in a way that reduces the impact of memory faults on the CiM-BNN’s inference accuracy, while preserving the correctness of the CiM operation. Concurrently, our technique encodes the CiM-BNN weights, securing them from weight theft. Our experiments on various CiM-BNNs show that BNN-Flip achieves an inference accuracy increase of up to 10.55% over the baseline (i.e. CiM-BNNs not employing BNN-Flip) in the presence of memory faults. Additionally, we show that the encoded weights generated by BNN-Flip furnish extremely low (near ‘random guess’) inference accuracy for the adversary attempting weight theft. The benefits of BNN-Flip come with an energy overhead of < 3%.","PeriodicalId":518586,"journal":{"name":"2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"54 7-8","pages":"146-152"},"PeriodicalIF":0.0,"publicationDate":"2024-01-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140530931","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An Efficient Transfer Learning Assisted Global Optimization Scheme for Analog/RF Circuits 模拟/射频电路的高效转移学习辅助全局优化方案

2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2024-01-22 DOI: 10.1109/ASP-DAC58780.2024.10473798

Zhikai Wang, Jingbo Zhou, Xiaosen Liu, Yan Wang

引用次数: 0

Towards a Highly Interactive Design-Debug-Verification Cycle 实现高度互动的设计-调试-验证循环

2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2024-01-22 DOI: 10.1109/ASP-DAC58780.2024.10473953

Lucas Klemmer Daniel, Daniel Große

{"title":"Towards a Highly Interactive Design-Debug-Verification Cycle","authors":"Lucas Klemmer Daniel, Daniel Große","doi":"10.1109/ASP-DAC58780.2024.10473953","DOIUrl":"https://doi.org/10.1109/ASP-DAC58780.2024.10473953","url":null,"abstract":"Taking a hardware design from concept to silicon is a long and complicated process, partly due to very long-running simulations. After modifying a Register Transfer Level (RTL) design, it is typically handed off to the simulator, which then simulates the full design for a given amount of time. If a bug is discovered, there is no way to adjust the design while still in the context of the simulation. Instead, all simulation results are thrown away, and the entire cycle must be restarted from the beginning.In this paper, we argue that it is worth breaking up this strict separation between design languages, analysis languages, verification languages, and simulators. We present virtual signals, a methodology to inject new logic into existing waveforms.Virtual signals are based on WAL, an open-source waveform analysis language, and can therefore use the capabilities of WAL for debugging, fixing, analyzing, and verifying a design. All this enables an interactive and fast response design-debug-verification cycle. To demonstrate the benefits of our methodology, we present a case-study in which we show how the technique improves debugging and design analysis.","PeriodicalId":518586,"journal":{"name":"2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"296 8","pages":"692-697"},"PeriodicalIF":0.0,"publicationDate":"2024-01-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140530960","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Resource-efficient Task Scheduling System using Reinforcement Learning : Invited Paper 利用强化学习的资源节约型任务调度系统：特邀论文

2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2024-01-22 DOI: 10.1109/ASP-DAC58780.2024.10473960

Chedi Morchdi, Cheng-Hsiang Chiu, Yi Zhou, Tsung-Wei Huang

引用次数: 0

On Decomposing Complex Test Cases for Efficient Post-silicon Validation 分解复杂测试用例，实现高效硅后验证

2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2024-01-22 DOI: 10.1109/ASP-DAC58780.2024.10473813

C. Harshitha, Sundarapalli Harikrishna, Peddakotla Rohith, Sandeep Chandran, Rajshekar Kalayappan

{"title":"On Decomposing Complex Test Cases for Efficient Post-silicon Validation","authors":"C. Harshitha, Sundarapalli Harikrishna, Peddakotla Rohith, Sandeep Chandran, Rajshekar Kalayappan","doi":"10.1109/ASP-DAC58780.2024.10473813","DOIUrl":"https://doi.org/10.1109/ASP-DAC58780.2024.10473813","url":null,"abstract":"In post-silicon validation, the first step when an erroneous behavior is uncovered by a long-running test case is to reproduce the observed behavior in a shorter execution. This makes it amenable to use a variety of tools and techniques to debug the error. In this work, we propose a tool called Gru, that takes a long execution trace as input and generates a set of executables, one for each section of the trace. Each generated executable is guaranteed to faithfully replicate the behavior observed in the corresponding section of the original, complex test case independently. This enables the generated executables to be run simultaneously across different silicon samples, thereby allowing further debugging activities to proceed in parallel. The generation of executables does not require the source code of the complex test case and hence supports privacy-aware debugging in scenarios involving sensitive Intellectual Properties (IPs). We demonstrate the effectiveness of this tool on a collection of 10 EEMBC benchmarks that are executed on a bare-metal LEON3 SoC.","PeriodicalId":518586,"journal":{"name":"2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"166 2","pages":"256-261"},"PeriodicalIF":0.0,"publicationDate":"2024-01-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140531169","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

SPIRAL: Signal-Power Integrity Co-Analysis for High-Speed Inter-Chiplet Serial Links Validation SPIRAL：用于高速芯片间串行链路验证的信号-电源完整性协同分析

2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2024-01-22 DOI: 10.1109/ASP-DAC58780.2024.10473908

Xiao Dong, Songyu Sun, Yangfan Jiang, Jingtong Hu, Dawei Gao, Cheng Zhuo

{"title":"SPIRAL: Signal-Power Integrity Co-Analysis for High-Speed Inter-Chiplet Serial Links Validation","authors":"Xiao Dong, Songyu Sun, Yangfan Jiang, Jingtong Hu, Dawei Gao, Cheng Zhuo","doi":"10.1109/ASP-DAC58780.2024.10473908","DOIUrl":"https://doi.org/10.1109/ASP-DAC58780.2024.10473908","url":null,"abstract":"Chiplet has recently emerged as a promising solution to achieving further performance improvements by breaking down complex processors into modular components and communicating through high-speed inter-chiplet serial links. However, the ever-growing on-package routing density and data rates of such serial links inevitably lead to more complex and worse signal and power integrity issues than a large monolithic chip. This highly demands efficient analysis and validation tools to support robust design. In this paper, a signal-power integrity co-analysis framework for high-speed inter-chiplet serial links validation named SPIRAL is proposed. The framework first builds equivalent models for the links with a machine learning-based transmitter model and an impulse response based model for the channel and receiver: Then, the signal-power integrity is co-analyzed with a pulse response based method using the equivalent models. Experimental results show that SPIRAL yields eye diagrams with 0.82-1.85% mean relative error, while achieving $18-44 times$ speedup compared to a commercial SPICE.","PeriodicalId":518586,"journal":{"name":"2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"21 9","pages":"625-630"},"PeriodicalIF":0.0,"publicationDate":"2024-01-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140530650","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Timing Analysis beyond Complementary CMOS Logic Styles 互补 CMOS 逻辑类型之外的时序分析

2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2024-01-22 DOI: 10.1109/ASP-DAC58780.2024.10473842

J. Lappas, Mohamed Amine Riahi, C. Weis, Norbert Wehn, Sani Nassif

引用次数: 0