2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC)最新文献_第3页

A High Performance Detailed Router Based on Integer Programming with Adaptive Route Guides 基于整数编程和自适应路由指引的高性能详细路由器

2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2024-01-22 DOI: 10.1109/ASP-DAC58780.2024.10473934

Zhongdong Qi, Shizhe Hu, Qi Peng, Hailong You, Chao Han, Zhangming Zhu

引用次数: 0

In Medio Stat Virtus*: Combining Boolean and Pattern Matching In Medio Stat Virtus*：布尔匹配与模式匹配相结合

2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2024-01-22 DOI: 10.1109/ASP-DAC58780.2024.10473889

Gianluca Radi, A. Calvino, Giovanni De Micheli

引用次数: 0

TIUP: Effective Processor Verification with Tautology-Induced Universal Properties TIUP：利用同义反复通用特性进行有效处理器验证

2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2024-01-22 DOI: 10.1109/ASP-DAC58780.2024.10473912

Yufeng Li, Yiwei Ci, Qiusong Yang

引用次数: 0

Physics-Informed Learning for Versatile RRAM Reset and Retention Simulation 多用途 RRAM 重置和保持仿真的物理信息学习

2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2024-01-22 DOI: 10.1109/ASP-DAC58780.2024.10473856

Tianshu Hou, Yuan Ren, Wenyong Zhou, Can Li, Zhongrui Wang, Haibao Chen, Ngai Wong

{"title":"Physics-Informed Learning for Versatile RRAM Reset and Retention Simulation","authors":"Tianshu Hou, Yuan Ren, Wenyong Zhou, Can Li, Zhongrui Wang, Haibao Chen, Ngai Wong","doi":"10.1109/ASP-DAC58780.2024.10473856","DOIUrl":"https://doi.org/10.1109/ASP-DAC58780.2024.10473856","url":null,"abstract":"Resistive random-access memory (RRAM) constitutes an emerging and promising platform for compute-inmemory (CIM) edge AI. However, the switching mechanism and controllability of RRAM are still under debate owing to the influence of multiphysics. Although physics-informed neural networks (PINNs) are successful in achieving mesh-free multiphysics solutions in many applications, the resultant accuracy is not satisfactory in RRAM analyses. This work investigates the characteristics of RRAM devices - retention and reset transition which are described in terms of the dissolution of a conductive filament (CF) in 3-D axis-symmetric geometry. Specifically, we provide a novel neural network characterization of ion migration, Joule heating, and carrier transport, governed by the solutions of partial differential equations (PDEs). Motivated by physics-informed learning, the separation of variables (SOV) method and the neural tangent kernel (NTK) theory, we propose a customized 3-channel fully-connected network and a modified random Fourier feature (mRFF) embedding strategy to capture multiscale properties and appropriate frequency features of the self-consistent multiphysics solutions. The proposed model eliminates the need for grid meshing and temporal iterations widely used in RRAM analysis. Experiments then confirm its superior accuracy over competing physics-informed methods.","PeriodicalId":518586,"journal":{"name":"2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"381 1","pages":"746-751"},"PeriodicalIF":0.0,"publicationDate":"2024-01-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140531181","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

LIPSTICK: Corruptibility-Aware and Explainable Graph Neural Network-based Oracle-Less Attack on Logic Locking LIPSTICK：基于可破译和可解释图神经网络的逻辑锁定无谕攻击

2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2024-01-22 DOI: 10.1109/ASP-DAC58780.2024.10473982

Yeganeh Aghamohammadi, Amin Rezaei

{"title":"LIPSTICK: Corruptibility-Aware and Explainable Graph Neural Network-based Oracle-Less Attack on Logic Locking","authors":"Yeganeh Aghamohammadi, Amin Rezaei","doi":"10.1109/ASP-DAC58780.2024.10473982","DOIUrl":"https://doi.org/10.1109/ASP-DAC58780.2024.10473982","url":null,"abstract":"In a zero-trust fabless paradigm, designers are increasingly concerned about hardware-based attacks on the semiconductor supply chain. Logic locking is a design-for-trust method that adds extra key-controlled gates in the circuits to prevent hardware intellectual property theft and overproduction. While attackers have traditionally relied on an oracle to attack logic-locked circuits, machine learning attacks have shown the ability to retrieve the secret key even without access to an oracle. In this paper, we first examine the limitations of state-of-the-art machine learning attacks and argue that the use of key hamming distance as the sole model-guiding structural metric is not always useful. Then, we develop, train, and test a corruptibility-aware graph neural network-based oracle-less attack on logic locking that takes into consideration both the structure and the behavior of the circuits. Our model is explainable in the sense that we analyze what the machine learning model has interpreted in the training process and how it can perform a successful attack. Chip designers may find this information beneficial in securing their designs while avoiding incremental fixes.","PeriodicalId":518586,"journal":{"name":"2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"372 3","pages":"606-611"},"PeriodicalIF":0.0,"publicationDate":"2024-01-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140531182","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

SWAT: An Efficient Swin Transformer Accelerator Based on FPGA SWAT：基于 FPGA 的高效 Swin 变压器加速器

2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2024-01-22 DOI: 10.1109/ASP-DAC58780.2024.10473931

Qiwei Dong, Xiaoru Xie, Zhongfeng Wang

{"title":"SWAT: An Efficient Swin Transformer Accelerator Based on FPGA","authors":"Qiwei Dong, Xiaoru Xie, Zhongfeng Wang","doi":"10.1109/ASP-DAC58780.2024.10473931","DOIUrl":"https://doi.org/10.1109/ASP-DAC58780.2024.10473931","url":null,"abstract":"Swin Transformer achieves greater efficiency than Vision Transformer by utilizing local self-attention and shifted windows. However, existing hardware accelerators designed for Transformer have not been optimized for the unique computation flow and data reuse property in Swin Transformer, resulting in lower hardware utilization and extra memory accesses. To address this issue, we develop SWAT, an efficient Swin Transformer Accelerator based on FPGA. Firstly, to eliminate the redundant computations in shifted windows, a novel tiling strategy is employed, which helps the developed multiplier array to fully utilize the sparsity. Additionally, we deploy a dynamic pipeline interleaving dataflow, which not only reduces the processing latency but also maximizes data reuse, thereby decreasing access to memories. Furthermore, customized quantization strategies and approximate calculations for non-linear calculations are adopted to simplify the hardware complexity with negligible network accuracy loss. We implement SWAT on the Xilinx Alveo U50 platform and evaluate it with Swin-T on the ImageNet dataset. The proposed architecture can achieve improvements of $2.02 times sim 3.11 times$ in power efficiency compared to existing Transformer accelerators on FPGAs.","PeriodicalId":518586,"journal":{"name":"2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"340 2","pages":"515-520"},"PeriodicalIF":0.0,"publicationDate":"2024-01-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140531184","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Collaborative Coalescing of Redundant Memory Access for GPU System 为 GPU 系统协同聚合冗余内存访问

2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2024-01-22 DOI: 10.1109/ASP-DAC58780.2024.10473837

Fan Jiang, Chengeng Li, Wei Zhang, Jiang Xu

引用次数: 0

ZEBRA: A Zero-Bit Robust-Accumulation Compute-In-Memory Approach for Neural Network Acceleration Utilizing Different Bitwise Patterns ZEBRA：利用不同比特模式实现神经网络加速的零比特稳健累积计算内存方法

2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2024-01-22 DOI: 10.1109/ASP-DAC58780.2024.10473851

Yiming Chen, Guodong Yin, Hongtao Zhong, Ming-En Lee, Huazhong Yang, Sumitha George, Vijaykrishnan Narayanan, Xueqing Li

{"title":"ZEBRA: A Zero-Bit Robust-Accumulation Compute-In-Memory Approach for Neural Network Acceleration Utilizing Different Bitwise Patterns","authors":"Yiming Chen, Guodong Yin, Hongtao Zhong, Ming-En Lee, Huazhong Yang, Sumitha George, Vijaykrishnan Narayanan, Xueqing Li","doi":"10.1109/ASP-DAC58780.2024.10473851","DOIUrl":"https://doi.org/10.1109/ASP-DAC58780.2024.10473851","url":null,"abstract":"Deploying a lightweight quantized model in compute-in-memory (CIM) might result in significant accuracy degradation due to reduced signal-noise rate (SNR). To address this issue, this paper presents ZEBRA, a zero-bit robust-accumulation CIM approach, which utilizes bitwise zero patterns to compress computation with ultra-high resilience against noise due to circuit non-idealities, etc. First, ZEBRA provides a cross-level design that successfully exploits value-adaptive zero-bit patterns to improve the performance in robust 8-bit quantization dramatically. Second, ZEBRA presents a multi-level local computing unit circuit design to implement the bitwise sparsity pattern, which boosts the area/energy efficiency by 2x-4x compared with existing CIM works. Experiments demonstrate that ZEBRA can achieve <1.0% accuracy loss in CIFAR10/100 with typical noise, while conventional CIM works suffer from > 10% accuracy loss. Such robustness leads to much more stable accuracy for high-parallelism inference on large models in practice.","PeriodicalId":518586,"journal":{"name":"2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"68 3","pages":"153-158"},"PeriodicalIF":0.0,"publicationDate":"2024-01-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140531046","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Microscope: Causality Inference Crossing the Hardware and Software Boundary from Hardware Perspective 显微镜：从硬件角度看跨越硬件和软件界限的因果推理

2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2024-01-22 DOI: 10.1109/ASP-DAC58780.2024.10473793

Zhaoxiang Liu, Kejun Chen, Dean Sullivan, Orlando Arias, R. Dutta, Yier Jin, Xiaolong Guo

{"title":"Microscope: Causality Inference Crossing the Hardware and Software Boundary from Hardware Perspective","authors":"Zhaoxiang Liu, Kejun Chen, Dean Sullivan, Orlando Arias, R. Dutta, Yier Jin, Xiaolong Guo","doi":"10.1109/ASP-DAC58780.2024.10473793","DOIUrl":"https://doi.org/10.1109/ASP-DAC58780.2024.10473793","url":null,"abstract":"The increasing complexity of System-on-Chip (SoC) designs and the rise of third-party vendors in the semiconductor industry have led to unprecedented security concerns. Traditional formal methods struggle to address software-exploited hardware bugs, and existing solutions for hardware-software co-verification often fall short. This paper presents Microscope, a novel framework for inferring software instruction patterns that can trigger hardware vulnerabilities in SoC designs. Microscope enhances the Structural Causal Model (SCM) with hardware features, creating a scalable Hardware Structural Causal Model (HW-SCM). A domain-specific language (DSL) in SMT-LIB represents the HW-SCM and predefined security properties, with incremental SMT solving deducing possible instructions. Microscope identifies causality to determine whether a hardware threat could result from any software events, providing a valuable resource for patching hardware bugs and generating test input. Extensive experimentation demonstrates Microscope’s capability to infer the causality of a wide range of vulnerabilities and bugs located in SoC-level benchmarks.","PeriodicalId":518586,"journal":{"name":"2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"288 16-17","pages":"933-938"},"PeriodicalIF":0.0,"publicationDate":"2024-01-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140530972","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Automated synthesis of mixed-signal ML inference hardware under accuracy constraints 精度限制下混合信号 ML 推理硬件的自动合成

2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2024-01-22 DOI: 10.1109/ASP-DAC58780.2024.10473942

K. Kunal, Jitesh Poojary, S. Ramprasath, Ramesh Harjani, S. Sapatnekar

引用次数: 0